/*
- * Copyright 2007 Freescale Semiconductor, Inc.
+ * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
#include <spd_sdram.h>
#include <netdev.h>
-#include "../common/pixis.h"
-
void sdram_init(void);
phys_size_t fixed_sdram(void);
void mpc8610hpcd_diu_init(void);
int misc_init_r(void)
{
u8 tmp_val, version;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
/*Do not use 8259PIC*/
- tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
- out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x80);
+ tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
+ out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);
/*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
- version = in8(PIXIS_BASE + PIXIS_PVER);
+ version = in_8(pixis_base + PIXIS_PVER);
if(version >= 0x07) {
- tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
- out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xbf);
+ tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
+ out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
}
/* Using this for DIU init before the driver in linux takes over
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
printf ("Board: MPC8610HPCD, System ID: 0x%02x, "
"System Version: 0x%02x, FPGA Version: 0x%02x\n",
- in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
- in8(PIXIS_BASE + PIXIS_PVER));
+ in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
+ in_8(pixis_base + PIXIS_PVER));
mcm->abcr |= 0x00010000; /* 0 */
mcm->hpmr3 = 0x80000008; /* 4c */
dram_size = fixed_sdram();
#endif
-#if defined(CONFIG_SYS_RAMBOOT)
- puts(" DDR: ");
- return dram_size;
-#endif
+ setup_ddr_bat(dram_size);
puts(" DDR: ");
return dram_size;
static struct pci_controller pcie2_hose;
#endif
-int first_free_busno = 0;
-
void pci_init_board(void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
- uint devdisr = gur->devdisr;
- uint io_sel = (gur->pordevsr & MPC8610_PORDEVSR_IO_SEL)
- >> MPC8610_PORDEVSR_IO_SEL_SHIFT;
- uint host_agent = (gur->porbmsr & MPC8610_PORBMSR_HA)
- >> MPC8610_PORBMSR_HA_SHIFT;
+ struct fsl_pci_info pci_info[3];
+ u32 devdisr, pordevsr, io_sel;
+ int first_free_busno = 0;
+ int num = 0;
- printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
- devdisr, io_sel, host_agent);
+ int pci_agent, pcie_ep, pcie_configured;
+
+ devdisr = in_be32(&gur->devdisr);
+ pordevsr = in_be32(&gur->pordevsr);
+ io_sel = (pordevsr & MPC8610_PORDEVSR_IO_SEL)
+ >> MPC8610_PORDEVSR_IO_SEL_SHIFT;
+
+ debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
#ifdef CONFIG_PCIE1
- {
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- struct pci_controller *hose = &pcie1_hose;
- int pcie_configured = (io_sel == 1) || (io_sel == 4);
- int pcie_ep = (host_agent == 0) || (host_agent == 2) ||
- (host_agent == 5);
- struct pci_region *r = hose->regions;
-
- if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) {
- printf(" PCIe 1 connected to Uli as %s (base address %x)\n",
- pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
- if (pci->pme_msg_det)
- pci->pme_msg_det = 0xffffffff;
-
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BUS,
- CONFIG_SYS_PCIE1_MEM_PHYS,
- CONFIG_SYS_PCIE1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_IO_BUS,
- CONFIG_SYS_PCIE1_IO_PHYS,
- CONFIG_SYS_PCIE1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno = first_free_busno;
- pci_setup_indirect(hose, (int)&pci->cfg_addr,
- (int)&pci->cfg_data);
-
- fsl_pci_init(hose);
-
- first_free_busno = hose->last_busno + 1;
- printf(" PCI-Express 1 on bus %02x - %02x\n",
- hose->first_busno, hose->last_busno);
-
- } else
- puts(" PCI-Express 1: Disabled\n");
- }
-#else
- puts("PCI-Express 1: Disabled\n");
-#endif /* CONFIG_PCIE1 */
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
+
+ if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)){
+ SET_STD_PCIE_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+ printf (" PCIE1 connected to ULI as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
+
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie1_hose, first_free_busno);
+ } else {
+ printf (" PCIE1: disabled\n");
+ }
+ puts("\n");
+#else
+ setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE1); /* disable */
+#endif
#ifdef CONFIG_PCIE2
- {
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
- struct pci_controller *hose = &pcie2_hose;
- struct pci_region *r = hose->regions;
-
- int pcie_configured = (io_sel == 0) || (io_sel == 4);
- int pcie_ep = (host_agent == 0) || (host_agent == 1) ||
- (host_agent == 4);
-
- if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) {
- printf(" PCI-Express 2 connected to slot as %s" \
- " (base address %x)\n",
- pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
- if (pci->pme_msg_det)
- pci->pme_msg_det = 0xffffffff;
-
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE2_MEM_BUS,
- CONFIG_SYS_PCIE2_MEM_PHYS,
- CONFIG_SYS_PCIE2_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE2_IO_BUS,
- CONFIG_SYS_PCIE2_IO_PHYS,
- CONFIG_SYS_PCIE2_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno = first_free_busno;
- pci_setup_indirect(hose, (int)&pci->cfg_addr,
- (int)&pci->cfg_data);
-
- fsl_pci_init(hose);
-
- first_free_busno = hose->last_busno + 1;
- printf(" PCI-Express 2 on bus %02x - %02x\n",
- hose->first_busno, hose->last_busno);
- } else
- puts(" PCI-Express 2: Disabled\n");
- }
-#else
- puts("PCI-Express 2: Disabled\n");
-#endif /* CONFIG_PCIE2 */
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
+
+ if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)){
+ SET_STD_PCIE_INFO(pci_info[num], 2);
+ pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
+ printf (" PCIE2 connected to Slot as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie2_hose, first_free_busno);
+ } else {
+ printf (" PCIE2: disabled\n");
+ }
+ puts("\n");
+#else
+ setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE2); /* disable */
+#endif
#ifdef CONFIG_PCI1
- {
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- struct pci_controller *hose = &pci1_hose;
- int pci_agent = (host_agent >= 4) && (host_agent <= 6);
- struct pci_region *r = hose->regions;
-
- if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) {
+ if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
+ SET_STD_PCI_INFO(pci_info[num], 1);
+ pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
printf(" PCI connected to PCI slots as %s" \
- " (base address %x)\n",
+ " (base address %lx)\n",
pci_agent ? "Agent" : "Host",
- (uint)pci);
-
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCI1_MEM_BUS,
- CONFIG_SYS_PCI1_MEM_PHYS,
- CONFIG_SYS_PCI1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCI1_IO_BUS,
- CONFIG_SYS_PCI1_IO_PHYS,
- CONFIG_SYS_PCI1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno = first_free_busno;
- pci_setup_indirect(hose, (int) &pci->cfg_addr,
- (int) &pci->cfg_data);
-
- fsl_pci_init(hose);
-
- first_free_busno = hose->last_busno + 1;
- printf(" PCI on bus %02x - %02x\n",
- hose->first_busno, hose->last_busno);
-
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pci1_hose, first_free_busno);
+ } else {
+ printf (" PCI: disabled\n");
+ }
- } else
- puts(" PCI: Disabled\n");
- }
-#endif /* CONFIG_PCI1 */
+ puts("\n");
+#else
+ setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */
+#endif
}
#if defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{
- do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
- "timebase-frequency", bd->bi_busfreq / 4, 1);
- do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
- "bus-frequency", bd->bi_busfreq, 1);
- do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
- "clock-frequency", bd->bi_intfreq, 1);
- do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
- "bus-frequency", bd->bi_busfreq, 1);
+ ft_cpu_setup(blob, bd);
- do_fixup_by_compat_u32(blob, "ns16550",
- "clock-frequency", bd->bi_busfreq, 1);
-
- fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize);
-
-#ifdef CONFIG_PCI1
- ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
-#endif
-#ifdef CONFIG_PCIE1
- ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
-#endif
-#ifdef CONFIG_PCIE2
- ft_fsl_pci_setup(blob, "pci2", &pcie2_hose);
-#endif
+ FT_FSL_PCI_SETUP;
}
#endif
{
u8 i;
ulong val = 0;
- ulong a;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
- a = PIXIS_BASE + PIXIS_SPD;
- i = in8(a);
+ i = in_8(pixis_base + PIXIS_SPD);
i &= 0x07;
switch (i) {
void board_reset(void)
{
- out8(PIXIS_BASE + PIXIS_RST, 0);
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+ out_8(pixis_base + PIXIS_RST, 0);
while (1)
;