/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008,2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
*/
#include <common.h>
-#include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
-static void
-get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
-{
- i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
-}
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 clk_adjust;
+ u32 cpo;
+ u32 write_data_delay;
+};
-unsigned int fsl_ddr_get_mem_data_rate(void)
-{
- return get_bus_freq(0);
-}
+/*
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+const struct board_specific_parameters dimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| clk| cpo|wrdata|2T
+ * ranks| mhz|adjst| | delay|
+ */
+ {4, 333, 7, 7, 3},
+ {4, 549, 7, 9, 3},
+ {4, 650, 7, 10, 4},
+ {2, 333, 7, 7, 3},
+ {2, 549, 7, 9, 3},
+ {2, 650, 7, 10, 4},
+ {1, 333, 7, 7, 3},
+ {1, 549, 7, 9, 3},
+ {1, 650, 7, 10, 4},
+ {}
+};
-void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
- unsigned int ctrl_num)
+/*
+ * The two slots have slightly different timing. The center values are good
+ * for both slots. We use identical speed tables for them. In future use, if
+ * DIMMs have fewer center values that require two separated tables, copy the
+ * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
+ */
+const struct board_specific_parameters *dimms[] = {
+ dimm0,
+ dimm0,
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
unsigned int i;
- unsigned int i2c_address = 0;
+ ulong ddr_freq;
+ if (ctrl_num > 1) {
+ printf("Wrong parameter for controller number %d", ctrl_num);
+ return;
+ }
for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
- if (ctrl_num == 0 && i == 0) {
- i2c_address = SPD_EEPROM_ADDRESS1;
- }
- if (ctrl_num == 0 && i == 1) {
- i2c_address = SPD_EEPROM_ADDRESS2;
- }
- if (ctrl_num == 1 && i == 0) {
- i2c_address = SPD_EEPROM_ADDRESS3;
- }
- if (ctrl_num == 1 && i == 1) {
- i2c_address = SPD_EEPROM_ADDRESS4;
- }
- get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+ if (pdimm[i].n_ranks)
+ break;
}
-}
+ if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */
+ return;
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- /*
- * Factors to consider for clock adjust:
- * - number of chips on bus
- * - position of slot
- * - DDR1 vs. DDR2?
- * - ???
- *
- * This needs to be determined on a board-by-board basis.
- * 0110 3/4 cycle late
- * 0111 7/8 cycle late
- */
- popts->clk_adjust = 7;
+ pbsp = dimms[ctrl_num];
- /*
- * Factors to consider for CPO:
- * - frequency
- * - ddr1 vs. ddr2
+ /* Get clk_adjust, cpo, write_data_delay, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
*/
- popts->cpo_override = 10;
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm[i].n_ranks) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
- /*
- * Factors to consider for write data delay:
- * - number of DIMMs
- *
- * 1 = 1/4 clock delay
- * 2 = 1/2 clock delay
- * 3 = 3/4 clock delay
- * 4 = 1 clock delay
- * 5 = 5/4 clock delay
- * 6 = 3/2 clock delay
- */
- popts->write_data_delay = 3;
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found "
+ "for data rate %lu MT/s!\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->cpo_override = pbsp_highest->cpo;
+ popts->write_data_delay = pbsp_highest->write_data_delay;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
+found:
+ /* 2T timing enable */
+ popts->twot_en = 1;
}
projects / u-boot / blobdiff