Merge branch 'master' of git://git.denx.de/u-boot-blackfin

[u-boot] / board / freescale / mpc8641hpcn / mpc8641hpcn.c

diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index fcaaacbee1ed9af0a43c00d241093399addadd71..0069b9cd471107aef89f1268823b19ec6d044ef7 100644 (file)
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -33,10 +33,6 @@
 
 #include "../common/pixis.h"
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
 long int fixed_sdram(void);
 
 int board_early_init_f(void)
@@ -70,13 +66,6 @@ initdram(int board_type)
        return dram_size;
 #endif
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-       /*
-        * Initialize and enable DDR ECC.
-        */
-       ddr_enable_ecc(dram_size);
-#endif
-
        puts("    DDR: ");
        return dram_size;
 }
@@ -161,6 +150,8 @@ static struct pci_controller pci2_hose;
 
 int first_free_busno = 0;
 
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
 
 void pci_init_board(void)
 {
@@ -173,8 +164,9 @@ void pci_init_board(void)
 #ifdef CONFIG_PCI1
 {
        volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
-       extern void fsl_pci_init(struct pci_controller *hose);
        struct pci_controller *hose = &pci1_hose;
+       struct pci_region *r = hose->regions;
+
 #ifdef DEBUG
        uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
                >> MPC8641_PORBMSR_HA_SHIFT;
@@ -193,27 +185,23 @@ void pci_init_board(void)
                debug("\n");
 
                /* inbound */
-               pci_set_region(hose->regions + 0,
-                              CONFIG_SYS_PCI_MEMORY_BUS,
-                              CONFIG_SYS_PCI_MEMORY_PHYS,
-                              CONFIG_SYS_PCI_MEMORY_SIZE,
-                              PCI_REGION_MEM | PCI_REGION_MEMORY);
+               r += fsl_pci_setup_inbound_windows(r);
 
                /* outbound memory */
-               pci_set_region(hose->regions + 1,
+               pci_set_region(r++,
                               CONFIG_SYS_PCI1_MEM_BASE,
                               CONFIG_SYS_PCI1_MEM_PHYS,
                               CONFIG_SYS_PCI1_MEM_SIZE,
                               PCI_REGION_MEM);
 
                /* outbound io */
-               pci_set_region(hose->regions + 2,
+               pci_set_region(r++,
                               CONFIG_SYS_PCI1_IO_BASE,
                               CONFIG_SYS_PCI1_IO_PHYS,
                               CONFIG_SYS_PCI1_IO_SIZE,
                               PCI_REGION_IO);
 
-               hose->region_count = 3;
+               hose->region_count = r - hose->regions;
 
                hose->first_busno=first_free_busno;
                pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
@@ -242,32 +230,27 @@ void pci_init_board(void)
 #ifdef CONFIG_PCI2
 {
        volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
-       extern void fsl_pci_init(struct pci_controller *hose);
        struct pci_controller *hose = &pci2_hose;
-
+       struct pci_region *r = hose->regions;
 
        /* inbound */
-       pci_set_region(hose->regions + 0,
-                      CONFIG_SYS_PCI_MEMORY_BUS,
-                      CONFIG_SYS_PCI_MEMORY_PHYS,
-                      CONFIG_SYS_PCI_MEMORY_SIZE,
-                      PCI_REGION_MEM | PCI_REGION_MEMORY);
+       r += fsl_pci_setup_inbound_windows(r);
 
        /* outbound memory */
-       pci_set_region(hose->regions + 1,
+       pci_set_region(r++,
                       CONFIG_SYS_PCI2_MEM_BASE,
                       CONFIG_SYS_PCI2_MEM_PHYS,
                       CONFIG_SYS_PCI2_MEM_SIZE,
                       PCI_REGION_MEM);
 
        /* outbound io */
-       pci_set_region(hose->regions + 2,
+       pci_set_region(r++,
                       CONFIG_SYS_PCI2_IO_BASE,
                       CONFIG_SYS_PCI2_IO_PHYS,
                       CONFIG_SYS_PCI2_IO_SIZE,
                       PCI_REGION_IO);
 
-       hose->region_count = 3;
+       hose->region_count = r - hose->regions;
 
        hose->first_busno=first_free_busno;
        pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
@@ -286,33 +269,20 @@ void pci_init_board(void)
 
 
 #if defined(CONFIG_OF_BOARD_SETUP)
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+                        struct pci_controller *hose);
 
 void
 ft_board_setup(void *blob, bd_t *bd)
 {
-       int node, tmp[2];
-       const char *path;
-
        ft_cpu_setup(blob, bd);
 
-       node = fdt_path_offset(blob, "/aliases");
-       tmp[0] = 0;
-       if (node >= 0) {
 #ifdef CONFIG_PCI1
-               path = fdt_getprop(blob, node, "pci0", NULL);
-               if (path) {
-                       tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
-                       do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
-               }
+       ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
 #endif
 #ifdef CONFIG_PCI2
-               path = fdt_getprop(blob, node, "pci1", NULL);
-               if (path) {
-                       tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
-                       do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
-               }
+       ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
 #endif
-       }
 }
 #endif