libfdt: migrate include/libfdt_env.h to a wrapper

[u-boot] / board / freescale / mx25pdk / mx25pdk.c

diff --git a/board/freescale/mx25pdk/mx25pdk.c b/board/freescale/mx25pdk/mx25pdk.c
index ebe3bcb6edddd0687e5cb8c38fd3d3d542e25b52..cab769cbd0b5568ca601f4e376a34726ce0b3dc2 100644 (file)
--- a/board/freescale/mx25pdk/mx25pdk.c
+++ b/board/freescale/mx25pdk/mx25pdk.c
@@ -138,7 +138,7 @@ int board_late_init(void)
 
        mx25pdk_fec_init();
 
-       ret = pmic_init(I2C_PMIC);
+       ret = pmic_init(I2C_0);
        if (ret)
                return ret;
 
@@ -146,8 +146,8 @@ int board_late_init(void)
        if (!p)
                return -ENODEV;
 
-       /* Turn on Ethernet PHY supply */
-       pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE);
+       /* Turn on Ethernet PHY and LCD supplies */
+       pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE | ONOFFA);
 
        return 0;
 }
@@ -175,6 +175,12 @@ int board_mmc_init(bd_t *bis)
 
        imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
 
+       /*
+        * Set the eSDHC1 PER clock to the maximum frequency lower than or equal
+        * to 50 MHz that can be obtained, which requires to use UPLL as the
+        * clock source. This actually gives 48 MHz.
+        */
+       imx_set_perclk(MXC_ESDHC1_CLK, true, 50000000);
        esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
        return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 }
@@ -186,3 +192,6 @@ int checkboard(void)
 
        return 0;
 }
+
+/* Lowlevel init isn't used on mx25pdk, so just provide a dummy one here */
+void lowlevel_init(void) {}