Merge branch 'master' of git://git.denx.de/u-boot-arm

[u-boot] / board / freescale / mx51evk / mx51evk.c

diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c
index 94ea1f29051fc675b4de614a778f0ee63c1c5da2..e5b0929f65e0b4641373127e5072805f25713436 100644 (file)
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -32,13 +32,12 @@
 #include <i2c.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
+#include <pmic.h>
 #include <fsl_pmic.h>
 #include <mc13892.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static u32 system_rev;
-
 #ifdef CONFIG_FSL_ESDHC
 struct fsl_esdhc_cfg esdhc_cfg[2] = {
        {MMC_SDHC1_BASE_ADDR, 1},
@@ -46,11 +45,6 @@ struct fsl_esdhc_cfg esdhc_cfg[2] = {
 };
 #endif
 
-u32 get_board_rev(void)
-{
-       return system_rev;
-}
-
 int dram_init(void)
 {
        /* dram_init must store complete ramsize in gd->ram_size */
@@ -182,34 +176,38 @@ static void power_init(void)
 {
        unsigned int val;
        struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+       struct pmic *p;
+
+       pmic_init();
+       p = get_pmic();
 
        /* Write needed to Power Gate 2 register */
-       val = pmic_reg_read(REG_POWER_MISC);
+       pmic_reg_read(p, REG_POWER_MISC, &val);
        val &= ~PWGT2SPIEN;
-       pmic_reg_write(REG_POWER_MISC, val);
+       pmic_reg_write(p, REG_POWER_MISC, val);
 
        /* Externally powered */
-       val = pmic_reg_read(REG_CHARGE);
+       pmic_reg_read(p, REG_CHARGE, &val);
        val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
-       pmic_reg_write(REG_CHARGE, val);
+       pmic_reg_write(p, REG_CHARGE, val);
 
        /* power up the system first */
-       pmic_reg_write(REG_POWER_MISC, PWUP);
+       pmic_reg_write(p, REG_POWER_MISC, PWUP);
 
        /* Set core voltage to 1.1V */
-       val = pmic_reg_read(REG_SW_0);
+       pmic_reg_read(p, REG_SW_0, &val);
        val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
-       pmic_reg_write(REG_SW_0, val);
+       pmic_reg_write(p, REG_SW_0, val);
 
        /* Setup VCC (SW2) to 1.25 */
-       val = pmic_reg_read(REG_SW_1);
+       pmic_reg_read(p, REG_SW_1, &val);
        val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
-       pmic_reg_write(REG_SW_1, val);
+       pmic_reg_write(p, REG_SW_1, val);
 
        /* Setup 1V2_DIG1 (SW3) to 1.25 */
-       val = pmic_reg_read(REG_SW_2);
+       pmic_reg_read(p, REG_SW_2, &val);
        val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
-       pmic_reg_write(REG_SW_2, val);
+       pmic_reg_write(p, REG_SW_2, val);
        udelay(50);
 
        /* Raise the core frequency to 800MHz */
@@ -217,47 +215,45 @@ static void power_init(void)
 
        /* Set switchers in Auto in NORMAL mode & STANDBY mode */
        /* Setup the switcher mode for SW1 & SW2*/
-       val = pmic_reg_read(REG_SW_4);
+       pmic_reg_read(p, REG_SW_4, &val);
        val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
                (SWMODE_MASK << SWMODE2_SHIFT)));
        val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
                (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
-       pmic_reg_write(REG_SW_4, val);
+       pmic_reg_write(p, REG_SW_4, val);
 
        /* Setup the switcher mode for SW3 & SW4 */
-       val = pmic_reg_read(REG_SW_5);
+       pmic_reg_read(p, REG_SW_5, &val);
        val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
                (SWMODE_MASK << SWMODE4_SHIFT)));
        val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
                (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
-       pmic_reg_write(REG_SW_5, val);
+       pmic_reg_write(p, REG_SW_5, val);
 
        /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
-       val = pmic_reg_read(REG_SETTING_0);
+       pmic_reg_read(p, REG_SETTING_0, &val);
        val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
        val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
-       pmic_reg_write(REG_SETTING_0, val);
+       pmic_reg_write(p, REG_SETTING_0, val);
 
        /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
-       val = pmic_reg_read(REG_SETTING_1);
+       pmic_reg_read(p, REG_SETTING_1, &val);
        val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
        val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
-       pmic_reg_write(REG_SETTING_1, val);
+       pmic_reg_write(p, REG_SETTING_1, val);
 
        /* Configure VGEN3 and VCAM regulators to use external PNP */
        val = VGEN3CONFIG | VCAMCONFIG;
-       pmic_reg_write(REG_MODE_1, val);
+       pmic_reg_write(p, REG_MODE_1, val);
        udelay(200);
 
-       gpio_direction_output(46, 0);
-
-       /* Reset the ethernet controller over GPIO */
-       writel(0x1, IOMUXC_BASE_ADDR + 0x0AC);
-
        /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
        val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
                VVIDEOEN | VAUDIOEN  | VSDEN;
-       pmic_reg_write(REG_MODE_1, val);
+       pmic_reg_write(p, REG_MODE_1, val);
+
+       mxc_request_iomux(MX51_PIN_EIM_A20, IOMUX_CONFIG_ALT1);
+       gpio_direction_output(46, 0);
 
        udelay(500);
 
@@ -269,6 +265,9 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc)
 {
        struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 
+       mxc_request_iomux(MX51_PIN_GPIO1_0, IOMUX_CONFIG_ALT1);
+       mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
+
        if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
                *cd = gpio_get_value(0);
        else
@@ -401,16 +400,13 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
-       system_rev = get_cpu_rev();
-
-       gd->bd->bi_arch_number = MACH_TYPE_MX51_BABBAGE;
        /* address of boot parameters */
        gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 
        return 0;
 }
 
-#ifdef BOARD_LATE_INIT
+#ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
 #ifdef CONFIG_MXC_SPI