mx6qsabrelite: search mii phy address 4-7

[u-boot] / board / freescale / mx6qsabresd / mx6qsabresd.c

diff --git a/board/freescale/mx6qsabresd/mx6qsabresd.c b/board/freescale/mx6qsabresd/mx6qsabresd.c
index 069c66417bd152900b981c99e2e341879433bc29..65c4a1a4f3cd4b67579a6cc2348a796a96bb0d51 100644 (file)
--- a/board/freescale/mx6qsabresd/mx6qsabresd.c
+++ b/board/freescale/mx6qsabresd/mx6qsabresd.c
@@ -51,12 +51,12 @@ int dram_init(void)
        return 0;
 }
 
-iomux_v3_cfg_t uart1_pads[] = {
+iomux_v3_cfg_t const uart1_pads[] = {
        MX6Q_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
        MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
-iomux_v3_cfg_t enet_pads[] = {
+iomux_v3_cfg_t const enet_pads[] = {
        MX6Q_PAD_ENET_MDIO__ENET_MDIO           | MUX_PAD_CTRL(ENET_PAD_CTRL),
        MX6Q_PAD_ENET_MDC__ENET_MDC             | MUX_PAD_CTRL(ENET_PAD_CTRL),
        MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC      | MUX_PAD_CTRL(ENET_PAD_CTRL),
@@ -86,37 +86,110 @@ static void setup_iomux_enet(void)
        gpio_set_value(IMX_GPIO_NR(1, 25), 1);
 }
 
-iomux_v3_cfg_t usdhc3_pads[] = {
+iomux_v3_cfg_t const usdhc2_pads[] = {
+       MX6Q_PAD_SD2_CLK__USDHC2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD2_CMD__USDHC2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD2_DAT0__USDHC2_DAT0  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD2_DAT1__USDHC2_DAT1  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD2_DAT2__USDHC2_DAT2  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD2_DAT3__USDHC2_DAT3  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_NANDF_D4__USDHC2_DAT4  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_NANDF_D5__USDHC2_DAT5  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_NANDF_D6__USDHC2_DAT6  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_NANDF_D7__USDHC2_DAT7  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_NANDF_D2__GPIO_2_2     | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+iomux_v3_cfg_t const usdhc3_pads[] = {
        MX6Q_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6Q_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6Q_PAD_NANDF_D0__GPIO_2_0    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 };
 
+iomux_v3_cfg_t const usdhc4_pads[] = {
+       MX6Q_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
 static void setup_iomux_uart(void)
 {
        imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 }
 
 #ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg usdhc_cfg[1] = {
+struct fsl_esdhc_cfg usdhc_cfg[3] = {
+       {USDHC2_BASE_ADDR},
        {USDHC3_BASE_ADDR},
+       {USDHC4_BASE_ADDR},
 };
 
+#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
+#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
+
 int board_mmc_getcd(struct mmc *mmc)
 {
-       gpio_direction_input(IMX_GPIO_NR(2, 0));
-       return !gpio_get_value(IMX_GPIO_NR(2, 0));
+       struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+       switch (cfg->esdhc_base) {
+       case USDHC2_BASE_ADDR:
+               return !gpio_get_value(USDHC2_CD_GPIO);
+       case USDHC3_BASE_ADDR:
+               return !gpio_get_value(USDHC3_CD_GPIO);
+       default:
+               return 1; /* eMMC/uSDHC4 is always present */
+       }
 }
 
 int board_mmc_init(bd_t *bis)
 {
-       imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+       int i;
+
+       for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+               switch (i) {
+               case 0:
+                       imx_iomux_v3_setup_multiple_pads(
+                               usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+                       gpio_direction_input(USDHC2_CD_GPIO);
+                       usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+                       break;
+               case 1:
+                       imx_iomux_v3_setup_multiple_pads(
+                               usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+                       gpio_direction_input(USDHC3_CD_GPIO);
+                       usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+                       break;
+               case 2:
+                       imx_iomux_v3_setup_multiple_pads(
+                               usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+                       usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+                       break;
+               default:
+                       printf("Warning: you configured more USDHC controllers"
+                               "(%d) than supported by the board\n", i + 1);
+                       return 0;
+              }
+
+              if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
+                       printf("Warning: failed to initialize mmc dev %d\n", i);
+       }
 
-       return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+       return 0;
 }
 #endif