Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

[u-boot] / board / freescale / mx6sabresd / mx6sabresd.c

diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index db9fdff92d87616b62cad26fdfd4b575f9e7ee78..d7d932eeb8a3fd70c7d78a6b41cd016cc811d5f8 100644 (file)
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -37,6 +37,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                  \
        PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+                     PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
 int dram_init(void)
 {
        gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -120,6 +123,34 @@ iomux_v3_cfg_t const usdhc4_pads[] = {
        MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 };
 
+iomux_v3_cfg_t const ecspi1_pads[] = {
+       MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_spi(void)
+{
+       imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+}
+
+iomux_v3_cfg_t const pcie_pads[] = {
+       MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),        /* POWER */
+       MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),        /* RESET */
+};
+
+static void setup_pcie(void)
+{
+       imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
+}
+
+iomux_v3_cfg_t const di0_pads[] = {
+       MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,        /* DISP0_CLK */
+       MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,               /* DISP0_HSYNC */
+       MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,               /* DISP0_VSYNC */
+};
+
 static void setup_iomux_uart(void)
 {
        imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
@@ -273,15 +304,15 @@ static void enable_lvds(struct display_info_t const *dev)
        struct iomuxc *iomux = (struct iomuxc *)
                                IOMUXC_BASE_ADDR;
        u32 reg = readl(&iomux->gpr[2]);
-       reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
-              IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT;
+       reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
+              IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT;
        writel(reg, &iomux->gpr[2]);
 }
 
 static struct display_info_t const displays[] = {{
        .bus    = -1,
        .addr   = 0,
-       .pixfmt = IPU_PIX_FMT_LVDS666,
+       .pixfmt = IPU_PIX_FMT_RGB666,
        .detect = NULL,
        .enable = enable_lvds,
        .mode   = {
@@ -371,11 +402,14 @@ static void setup_display(void)
        struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
        int reg;
 
+       /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
+       imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));
+
        enable_ipu_clock();
        imx_setup_hdmi();
 
        /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
-       reg = __raw_readl(&mxc_ccm->CCGR3);
+       reg = readl(&mxc_ccm->CCGR3);
        reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
        writel(reg, &mxc_ccm->CCGR3);
 
@@ -429,15 +463,10 @@ int overwrite_console(void)
 
 int board_eth_init(bd_t *bis)
 {
-       int ret;
-
        setup_iomux_enet();
+       setup_pcie();
 
-       ret = cpu_eth_init(bis);
-       if (ret)
-               printf("FEC MXC: %s:failed\n", __func__);
-
-       return ret;
+       return cpu_eth_init(bis);
 }
 
 int board_early_init_f(void)
@@ -455,6 +484,10 @@ int board_init(void)
        /* address of boot parameters */
        gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+#ifdef CONFIG_MXC_SPI
+       setup_spi();
+#endif
+
        return 0;
 }