Merge git://git.denx.de/u-boot-mpc85xx

[u-boot] / board / freescale / mx6sxsabresd / mx6sxsabresd.c

diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 2ff960e3bb784149ccc2650f5e8700b3a9ee8a4d..0460cd9257b15196288a17cac35a130f9205f390 100644 (file)
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -27,7 +27,7 @@
 #include <power/pfuze100_pmic.h>
 #include "../common/pfuze.h"
 #include <usb.h>
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -59,9 +59,12 @@ DECLARE_GLOBAL_DATA_PTR;
        PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
        PAD_CTL_ODE)
 
+#define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+       PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
+
 int dram_init(void)
 {
-       gd->ram_size = PHYS_SDRAM_SIZE;
+       gd->ram_size = imx_ddr_size();
 
        return 0;
 }
@@ -150,11 +153,15 @@ static int setup_fec(void)
 {
        struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
        struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
-       int reg;
+       int reg, ret;
 
        /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
        clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
 
+       ret = enable_fec_anatop_clock(0, ENET_125MHZ);
+       if (ret)
+               return ret;
+
        imx_iomux_v3_setup_multiple_pads(phy_control_pads,
                                         ARRAY_SIZE(phy_control_pads));
 
@@ -163,14 +170,14 @@ static int setup_fec(void)
 
        /* Reset AR8031 PHY */
        gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
-       udelay(500);
+       mdelay(10);
        gpio_set_value(IMX_GPIO_NR(2, 7), 1);
 
        reg = readl(&anatop->pll_enet);
        reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
        writel(reg, &anatop->pll_enet);
 
-       return enable_fec_anatop_clock(ENET_125MHZ);
+       return 0;
 }
 
 int board_eth_init(bd_t *bis)
@@ -199,7 +206,8 @@ static struct i2c_pads_info i2c_pad_info1 = {
 int power_init_board(void)
 {
        struct pmic *p;
-       unsigned int reg, ret;
+       unsigned int reg;
+       int ret;
 
        p = pfuze_common_init(I2C_PMIC);
        if (!p)
@@ -308,6 +316,11 @@ static struct fsl_esdhc_cfg usdhc_cfg[3] = {
 #define USDHC3_PWR_GPIO        IMX_GPIO_NR(2, 11)
 #define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21)
 
+int board_mmc_get_env_dev(int devno)
+{
+       return devno - 1;
+}
+
 int board_mmc_getcd(struct mmc *mmc)
 {
        struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
@@ -335,7 +348,7 @@ int board_mmc_init(bd_t *bis)
 
        /*
         * According to the board_mmc_init() the following map is done:
-        * (U-boot device node)    (Physical Port)
+        * (U-Boot device node)    (Physical Port)
         * mmc0                    USDHC2
         * mmc1                    USDHC3
         * mmc2                    USDHC4
@@ -453,6 +466,60 @@ int board_qspi_init(void)
 }
 #endif
 
+#ifdef CONFIG_VIDEO_MXS
+static iomux_v3_cfg_t const lcd_pads[] = {
+       MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
+       MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
+       MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+       MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+       MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+       MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+       MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+       MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+       MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+       MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+       MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+       MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+       MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+       MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+       MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+       MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+       MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+       MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+       MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+       MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+       MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+       MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+       MX6_PAD_LCD1_DATA18__LCDIF1_DATA_18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+       MX6_PAD_LCD1_DATA19__LCDIF1_DATA_19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+       MX6_PAD_LCD1_DATA20__LCDIF1_DATA_20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+       MX6_PAD_LCD1_DATA21__LCDIF1_DATA_21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+       MX6_PAD_LCD1_DATA22__LCDIF1_DATA_22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+       MX6_PAD_LCD1_DATA23__LCDIF1_DATA_23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+       MX6_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+       /* Use GPIO for Brightness adjustment, duty cycle = period */
+       MX6_PAD_SD1_DATA2__GPIO6_IO_4 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static int setup_lcd(void)
+{
+       enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
+
+       imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+
+       /* Reset the LCD */
+       gpio_direction_output(IMX_GPIO_NR(3, 27) , 0);
+       udelay(500);
+       gpio_direction_output(IMX_GPIO_NR(3, 27) , 1);
+
+       /* Set Brightness to high */
+       gpio_direction_output(IMX_GPIO_NR(6, 4) , 1);
+
+       return 0;
+}
+#endif
+
 int board_init(void)
 {
        /* Address of boot parameters */
@@ -466,6 +533,10 @@ int board_init(void)
        board_qspi_init();
 #endif
 
+#ifdef CONFIG_VIDEO_MXS
+       setup_lcd();
+#endif
+
        return 0;
 }
 
@@ -565,6 +636,9 @@ static void spl_dram_init(void)
                .bi_on = 1,             /* Bank interleaving enabled */
                .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
                .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
+               .ddr_type = DDR_TYPE_DDR3,
+               .refsel = 1,    /* Refresh cycles at 32KHz */
+               .refr = 7,      /* 8 refresh commands per refresh cycle */
        };
 
        mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
@@ -596,8 +670,4 @@ void board_init_f(ulong dummy)
        /* load/boot image from boot device */
        board_init_r(NULL, 0);
 }
-
-void reset_cpu(ulong addr)
-{
-}
 #endif