]> git.sur5r.net Git - u-boot/blobdiff - board/freescale/p1010rdb/tlb.c
board/p1010rdb:Add NAND boot support using new SPL format
[u-boot] / board / freescale / p1010rdb / tlb.c
index 4256bf4e5707aec43b6cbc4bed5afed3aa8e493d..7a8690a90d90dacb3128fdc256057807bc157dd5 100644 (file)
@@ -43,16 +43,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
        /* TLB 1 */
        /* *I*** - Covers boot page */
-       SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                       0, 0, BOOKE_PAGESZ_4K, 1),
+       SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 0, BOOKE_PAGESZ_8K, 1),
 
        /* *I*G* - CCSRBAR */
        SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
                        MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 1, BOOKE_PAGESZ_1M, 1),
 
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
 #ifndef CONFIG_SDCARD
        SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
                        MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
@@ -64,7 +64,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
                        0, 3, BOOKE_PAGESZ_16M, 1),
 #endif
 
-#ifdef CONFIG_PCI
+#ifndef CONFIG_PCI
        /* *I*G* - PCI */
        SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
                        MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -88,7 +88,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
                        0, 7, BOOKE_PAGESZ_1M, 1),
 #endif
 
-#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
                        MAS3_SX|MAS3_SW|MAS3_SR, 0,
                        0, 8, BOOKE_PAGESZ_1G, 1)