SPDX: Convert all of our single license tags to Linux Kernel style

[u-boot] / board / freescale / p1022ds / ddr.c

diff --git a/board/freescale/p1022ds/ddr.c b/board/freescale/p1022ds/ddr.c
index 20b996e52a9872f27eefff66752d32796f7edcd1..70932115f4b9ee88910f87ad415cd800758d3f31 100644 (file)
--- a/board/freescale/p1022ds/ddr.c
+++ b/board/freescale/p1022ds/ddr.c
@@ -1,75 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2010 Freescale Semiconductor, Inc.
  * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
  *          Timur Tabi <timur@freescale.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
  */
 
 #include <common.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
-typedef struct {
-       u32 datarate_mhz_low;
-       u32 datarate_mhz_high;
+struct board_specific_parameters {
        u32 n_ranks;
+       u32 datarate_mhz_high;
        u32 clk_adjust;         /* Range: 0-8 */
        u32 cpo;                /* Range: 2-31 */
        u32 write_data_delay;   /* Range: 0-6 */
-       u32 force_2T;
-} board_specific_parameters_t;
+       u32 force_2t;
+};
 
-static const board_specific_parameters_t bsp[] = {
 /*
- *        lo|  hi|  num|  clk| cpo|wrdata|2T
- *       mhz| mhz|ranks|adjst|    | delay|
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
  */
-       {  0, 333,    1,    5,  31,     3, 0},
-       {334, 400,    1,    5,  31,     3, 0},
-       {401, 549,    1,    5,  31,     3, 0},
-       {550, 680,    1,    5,  31,     5, 0},
-       {681, 850,    1,    5,  31,     5, 0},
-       {  0, 333,    2,    5,  31,     3, 0},
-       {334, 400,    2,    5,  31,     3, 0},
-       {401, 549,    2,    5,  31,     3, 0},
-       {550, 680,    2,    5,  31,     5, 0},
-       {681, 850,    2,    5,  31,     5, 0},
+static const struct board_specific_parameters dimm0[] = {
+       /*
+        * memory controller 0
+        *   num|  hi|  clk| cpo|wrdata|2T
+        * ranks| mhz|adjst|    | delay|
+        */
+       {1,  549,    5,  31,     3, 0},
+       {1,  850,    5,  31,     5, 0},
+       {2,  549,    5,  31,     3, 0},
+       {2,  850,    5,  31,     5, 0},
+       {}
 };
 
 void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
                           unsigned int ctrl_num)
 {
+       const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
        unsigned long ddr_freq;
        unsigned int i;
 
+
+       if (ctrl_num) {
+               printf("Wrong parameter for controller number %d", ctrl_num);
+               return;
+       }
+       if (!pdimm->n_ranks)
+               return;
+
        /* set odt_rd_cfg and odt_wr_cfg. */
        for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
                popts->cs_local_opts[i].odt_rd_cfg = 0;
                popts->cs_local_opts[i].odt_wr_cfg = 1;
        }
 
+       pbsp = dimm0;
        /*
         * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
         * freqency and n_banks specified in board_specific_parameters table.
         */
        ddr_freq = get_ddr_freq(0) / 1000000;
-       for (i = 0; i < ARRAY_SIZE(bsp); i++) {
-               if (ddr_freq >= bsp[i].datarate_mhz_low &&
-                   ddr_freq <= bsp[i].datarate_mhz_high &&
-                   pdimm->n_ranks == bsp[i].n_ranks) {
-                       popts->clk_adjust = bsp[i].clk_adjust;
-                       popts->cpo_override = bsp[i].cpo;
-                       popts->write_data_delay = bsp[i].write_data_delay;
-                       popts->twoT_en = bsp[i].force_2T;
-                       break;
+       while (pbsp->datarate_mhz_high) {
+               if (pbsp->n_ranks == pdimm->n_ranks) {
+                       if (ddr_freq <= pbsp->datarate_mhz_high) {
+                               popts->clk_adjust = pbsp->clk_adjust;
+                               popts->cpo_override = pbsp->cpo;
+                               popts->write_data_delay =
+                                       pbsp->write_data_delay;
+                               popts->twot_en = pbsp->force_2t;
+                               goto found;
+                       }
+                       pbsp_highest = pbsp;
                }
+               pbsp++;
+       }
+
+       if (pbsp_highest) {
+               printf("Error: board specific timing not found "
+                       "for data rate %lu MT/s!\n"
+                       "Trying to use the highest speed (%u) parameters\n",
+                       ddr_freq, pbsp_highest->datarate_mhz_high);
+               popts->clk_adjust = pbsp->clk_adjust;
+               popts->cpo_override = pbsp->cpo;
+               popts->write_data_delay = pbsp->write_data_delay;
+               popts->twot_en = pbsp->force_2t;
+       } else {
+               panic("DIMM is not supported by this board");
        }
 
+found:
        popts->half_strength_driver_enable = 1;
 
        /* Per AN4039, enable ZQ calibration. */