Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

[u-boot] / board / freescale / p1_p2_rdb_pc / ddr.c

diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
index 9355536b35d072a3a84f045db39fa5cf25045b7a..5c51845ddfc0e95e92b9197aff9fa7a12701e25d 100644 (file)
--- a/board/freescale/p1_p2_rdb_pc/ddr.c
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c
@@ -80,7 +80,7 @@ dimm_params_t ddr_raw_timing = {
        .refresh_rate_ps = 7800000,
        .tFAW_ps = 30000,
 };
-#elif defined(CONFIG_P1020MBG)
+#elif (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
 /* Micron MT41J512M8_187E */
 dimm_params_t ddr_raw_timing = {
        .n_ranks = 2,
@@ -111,7 +111,7 @@ dimm_params_t ddr_raw_timing = {
        .refresh_rate_ps = 7800000,
        .tFAW_ps = 37500,
 };
-#elif defined(CONFIG_P1020RDB)
+#elif defined(CONFIG_P1020RDB_PC)
 /*
  * Samsung K4B2G0846C-HCF8
  * The following timing are for "downshift"
@@ -251,7 +251,7 @@ phys_size_t fixed_sdram(void)
 
        ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 
-       fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+       fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
 
        if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
                                ddr_size, LAW_TRGT_IF_DDR_1) < 0) {