Merge branch 'master' of git://git.denx.de/u-boot-arm

[u-boot] / board / freescale / p1_p2_rdb_pc / ddr.c

diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
index 88ba56f457e92522b189423d1a462632acdcc304..946d5032e74616e71124329428b934789a66eb3c 100644 (file)
--- a/board/freescale/p1_p2_rdb_pc/ddr.c
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c
@@ -10,8 +10,8 @@
 #include <asm/mmu.h>
 #include <asm/immap_85xx.h>
 #include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 #include <asm/io.h>
 #include <asm/fsl_law.h>
 
@@ -34,20 +34,20 @@ dimm_params_t ddr_raw_timing = {
        .edc_config = 0,
        .burst_lengths_bitmask = 0x0c,
 
-       .tCKmin_X_ps = 1870,
-       .caslat_X = 0x1e << 4,  /* 5,6,7,8 */
-       .tAA_ps = 13125,
-       .tWR_ps = 15000,
-       .tRCD_ps = 13125,
-       .tRRD_ps = 7500,
-       .tRP_ps = 13125,
-       .tRAS_ps = 37500,
-       .tRC_ps = 50625,
-       .tRFC_ps = 160000,
-       .tWTR_ps = 7500,
-       .tRTP_ps = 7500,
+       .tckmin_x_ps = 1870,
+       .caslat_x = 0x1e << 4,  /* 5,6,7,8 */
+       .taa_ps = 13125,
+       .twr_ps = 15000,
+       .trcd_ps = 13125,
+       .trrd_ps = 7500,
+       .trp_ps = 13125,
+       .tras_ps = 37500,
+       .trc_ps = 50625,
+       .trfc_ps = 160000,
+       .twtr_ps = 7500,
+       .trtp_ps = 7500,
        .refresh_rate_ps = 7800000,
-       .tFAW_ps = 37500,
+       .tfaw_ps = 37500,
 };
 #elif defined(CONFIG_P2020RDB)
 /* Micron MT41J128M16_15E */
@@ -65,22 +65,22 @@ dimm_params_t ddr_raw_timing = {
        .edc_config = 0,
        .burst_lengths_bitmask = 0x0c,
 
-       .tCKmin_X_ps = 1500,
-       .caslat_X = 0x7e << 4,  /* 5,6,7,8,9,10 */
-       .tAA_ps = 13500,
-       .tWR_ps = 15000,
-       .tRCD_ps = 13500,
-       .tRRD_ps = 6000,
-       .tRP_ps = 13500,
-       .tRAS_ps = 36000,
-       .tRC_ps = 49500,
-       .tRFC_ps = 160000,
-       .tWTR_ps = 7500,
-       .tRTP_ps = 7500,
+       .tckmin_x_ps = 1500,
+       .caslat_x = 0x7e << 4,  /* 5,6,7,8,9,10 */
+       .taa_ps = 13500,
+       .twr_ps = 15000,
+       .trcd_ps = 13500,
+       .trrd_ps = 6000,
+       .trp_ps = 13500,
+       .tras_ps = 36000,
+       .trc_ps = 49500,
+       .trfc_ps = 160000,
+       .twtr_ps = 7500,
+       .trtp_ps = 7500,
        .refresh_rate_ps = 7800000,
-       .tFAW_ps = 30000,
+       .tfaw_ps = 30000,
 };
-#elif defined(CONFIG_P1020MBG)
+#elif (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
 /* Micron MT41J512M8_187E */
 dimm_params_t ddr_raw_timing = {
        .n_ranks = 2,
@@ -96,22 +96,22 @@ dimm_params_t ddr_raw_timing = {
        .edc_config = 0,
        .burst_lengths_bitmask = 0x0c,
 
-       .tCKmin_X_ps = 1870,
-       .caslat_X = 0x1e << 4,  /* 5,6,7,8 */
-       .tAA_ps = 13125,
-       .tWR_ps = 15000,
-       .tRCD_ps = 13125,
-       .tRRD_ps = 7500,
-       .tRP_ps = 13125,
-       .tRAS_ps = 37500,
-       .tRC_ps = 50625,
-       .tRFC_ps = 160000,
-       .tWTR_ps = 7500,
-       .tRTP_ps = 7500,
+       .tckmin_x_ps = 1870,
+       .caslat_x = 0x1e << 4,  /* 5,6,7,8 */
+       .taa_ps = 13125,
+       .twr_ps = 15000,
+       .trcd_ps = 13125,
+       .trrd_ps = 7500,
+       .trp_ps = 13125,
+       .tras_ps = 37500,
+       .trc_ps = 50625,
+       .trfc_ps = 160000,
+       .twtr_ps = 7500,
+       .trtp_ps = 7500,
        .refresh_rate_ps = 7800000,
-       .tFAW_ps = 37500,
+       .tfaw_ps = 37500,
 };
-#elif defined(CONFIG_P1020RDB)
+#elif defined(CONFIG_P1020RDB_PC)
 /*
  * Samsung K4B2G0846C-HCF8
  * The following timing are for "downshift"
@@ -133,20 +133,20 @@ dimm_params_t ddr_raw_timing = {
        .edc_config = 0,
        .burst_lengths_bitmask = 0x0c,
 
-       .tCKmin_X_ps = 1875,
-       .caslat_X = 0x1e << 4,  /* 5,6,7,8 */
-       .tAA_ps = 13125,
-       .tWR_ps = 15000,
-       .tRCD_ps = 13125,
-       .tRRD_ps = 7500,
-       .tRP_ps = 13125,
-       .tRAS_ps = 37500,
-       .tRC_ps = 50625,
-       .tRFC_ps = 160000,
-       .tWTR_ps = 7500,
-       .tRTP_ps = 7500,
+       .tckmin_x_ps = 1875,
+       .caslat_x = 0x1e << 4,  /* 5,6,7,8 */
+       .taa_ps = 13125,
+       .twr_ps = 15000,
+       .trcd_ps = 13125,
+       .trrd_ps = 7500,
+       .trp_ps = 13125,
+       .tras_ps = 37500,
+       .trc_ps = 50625,
+       .trfc_ps = 160000,
+       .twtr_ps = 7500,
+       .trtp_ps = 7500,
        .refresh_rate_ps = 7800000,
-       .tFAW_ps = 37500,
+       .tfaw_ps = 37500,
 };
 #elif  defined(CONFIG_P1024RDB) || \
        defined(CONFIG_P1025RDB)
@@ -171,20 +171,20 @@ dimm_params_t ddr_raw_timing = {
        .edc_config = 0,
        .burst_lengths_bitmask = 0x0c,
 
-       .tCKmin_X_ps = 1500,
-       .caslat_X = 0x3e << 4,  /* 5,6,7,8,9 */
-       .tAA_ps = 13125,
-       .tWR_ps = 15000,
-       .tRCD_ps = 13125,
-       .tRRD_ps = 6000,
-       .tRP_ps = 13125,
-       .tRAS_ps = 36000,
-       .tRC_ps = 49125,
-       .tRFC_ps = 160000,
-       .tWTR_ps = 7500,
-       .tRTP_ps = 7500,
+       .tckmin_x_ps = 1500,
+       .caslat_x = 0x3e << 4,  /* 5,6,7,8,9 */
+       .taa_ps = 13125,
+       .twr_ps = 15000,
+       .trcd_ps = 13125,
+       .trrd_ps = 6000,
+       .trp_ps = 13125,
+       .tras_ps = 36000,
+       .trc_ps = 49125,
+       .trfc_ps = 160000,
+       .twtr_ps = 7500,
+       .trtp_ps = 7500,
        .refresh_rate_ps = 7800000,
-       .tFAW_ps = 30000,
+       .tfaw_ps = 30000,
 };
 #else
 #error Missing raw timing data for this board
@@ -206,6 +206,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 }
 #endif /* CONFIG_SYS_DDR_RAW_TIMING */
 
+#ifdef CONFIG_SYS_DDR_CS0_BNDS
 /* Fixed sdram init -- doesn't use serial presence detect. */
 phys_size_t fixed_sdram(void)
 {
@@ -246,11 +247,11 @@ phys_size_t fixed_sdram(void)
 
        get_sys_info(&sysinfo);
        printf("Configuring DDR for %s MT/s data rate\n",
-                       strmhz(buf, sysinfo.freqDDRBus));
+                       strmhz(buf, sysinfo.freq_ddrbus));
 
        ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 
-       fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+       fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
 
        if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
                                ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
@@ -260,6 +261,7 @@ phys_size_t fixed_sdram(void)
 
        return ddr_size;
 }
+#endif
 
 void fsl_ddr_board_options(memctl_options_t *popts,
                                dimm_params_t *pdimm,