ARM: ls102xa: Setting device's stream id for SMMUs.

[u-boot] / board / freescale / p2020ds / ddr.c

diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c
index c43f874c92a5462974e087be8fe1d5fd01b01bc2..debe70b18b9a3d1813f4db56f9746d41d79a5ef2 100644 (file)
--- a/board/freescale/p2020ds/ddr.c
+++ b/board/freescale/p2020ds/ddr.c
@@ -8,8 +8,8 @@
 
 #include <common.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
 struct board_specific_parameters {
        u32 n_ranks;
@@ -17,7 +17,7 @@ struct board_specific_parameters {
        u32 clk_adjust;
        u32 cpo;
        u32 write_data_delay;
-       u32 force_2T;
+       u32 force_2t;
 };
 
 
@@ -37,7 +37,7 @@ static const struct board_specific_parameters dimm0[] = {
         *   num|  hi|  clk| cpo|wrdata|2T
         * ranks| mhz|adjst|    | delay|
         */
-#ifdef CONFIG_FSL_DDR2
+#ifdef CONFIG_SYS_FSL_DDR2
        {2,  549,    4,   0x1f,    2,  0},
        {2,  680,    4,   0x1f,    3,  0},
        {2,  850,    4,   0x1f,    4,  0},
@@ -57,6 +57,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 {
        const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
        ulong ddr_freq;
+       int i;
 
        if (ctrl_num) {
                printf("Wrong parameter for controller number %d", ctrl_num);
@@ -65,6 +66,17 @@ void fsl_ddr_board_options(memctl_options_t *popts,
        if (!pdimm->n_ranks)
                return;
 
+       /*
+        * set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
+        * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
+        * there are two dimms in the controller, set odt_rd_cfg to 3 and
+        * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
+        */
+       for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+               popts->cs_local_opts[i].odt_rd_cfg = 0;
+               popts->cs_local_opts[i].odt_wr_cfg = 1;
+       }
+
        pbsp = dimm0;
 
        /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
@@ -78,7 +90,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
                                popts->cpo_override = pbsp->cpo;
                                popts->write_data_delay =
                                        pbsp->write_data_delay;
-                               popts->twoT_en = pbsp->force_2T;
+                               popts->twot_en = pbsp->force_2t;
                                goto found;
                        }
                        pbsp_highest = pbsp;
@@ -94,7 +106,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
                popts->clk_adjust = pbsp_highest->clk_adjust;
                popts->cpo_override = pbsp_highest->cpo;
                popts->write_data_delay = pbsp_highest->write_data_delay;
-               popts->twoT_en = pbsp_highest->force_2T;
+               popts->twot_en = pbsp_highest->force_2t;
        } else {
                panic("DIMM is not supported by this board");
        }