powerpc/t4240qds: Print FPGA detail version

[u-boot] / board / freescale / p2020ds / p2020ds.c

diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index d3af6cf185167e3fc4af9b76f38d1ff1291b349d..d4a445108ad8eb55a9f1b9668676f0645dcb4065 100644 (file)
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2011 Freescale Semiconductor, Inc.
+ * Copyright 2007-2012 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -61,12 +61,8 @@ int checkboard(void)
 {
        u8 sw;
 
-       puts("Board: P2020DS ");
-#ifdef CONFIG_PHYS_64BIT
-       puts("(36-bit addrmap) ");
-#endif
-
-       printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+       printf("Board: P2020DS Sys ID: 0x%02x, "
+              "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
                in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
 
        sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
@@ -88,7 +84,7 @@ int checkboard(void)
 
 phys_size_t fixed_sdram(void)
 {
-       volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+       volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
        uint d_init;
 
        ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
@@ -261,6 +257,10 @@ void ft_board_setup(void *blob, bd_t *bd)
 
        fdt_fixup_memory(blob, (u64)base, (u64)size);
 
+#ifdef CONFIG_HAS_FSL_DR_USB
+       fdt_fixup_dr_usb(blob, bd);
+#endif
+
        FT_FSL_PCI_SETUP;
 
 #ifdef CONFIG_FSL_SGMII_RISER