powerpc/85xx: Rework P2020DS pci_init_board to use common FSL PCIe code

[u-boot] / board / freescale / p2020ds / tlb.c

diff --git a/board/freescale/p2020ds/tlb.c b/board/freescale/p2020ds/tlb.c
index 36ad086d0893a7de1df4ff2af1622e537e671a67..824b3b29f08aace97855143b6dd3f57b437db46a 100644 (file)
--- a/board/freescale/p2020ds/tlb.c
+++ b/board/freescale/p2020ds/tlb.c
@@ -28,19 +28,19 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
        /* TLB 0 - for temp stack in cache */
-       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
                      0, 0, BOOKE_PAGESZ_4K, 0),
        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-                     CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+                     CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
                      0, 0, BOOKE_PAGESZ_4K, 0),
        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-                     CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+                     CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
                      0, 0, BOOKE_PAGESZ_4K, 0),
        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-                     CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+                     CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
                      0, 0, BOOKE_PAGESZ_4K, 0),