board: ls1043ardb: move sec_init to board_init

[u-boot] / board / freescale / p2041rdb / cpld.h

diff --git a/board/freescale/p2041rdb/cpld.h b/board/freescale/p2041rdb/cpld.h
index dcdb410d8b6cc98b8281349481f161ed14177079..64487f1bf6d1abd72d6d4658a7fea1b7654c87ec 100644 (file)
--- a/board/freescale/p2041rdb/cpld.h
+++ b/board/freescale/p2041rdb/cpld.h
@@ -2,10 +2,7 @@
  * Copyright 2011 Freescale Semiconductor
  * Author: Mingkai Hu <Mingkai.hu@freescale.com>
  *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
+ * SPDX-License-Identifier:    GPL-2.0+
  *
  * This file provides support for the ngPIXIS, a board-specific FPGA used on
  * some Freescale reference boards.
@@ -19,7 +16,7 @@ typedef struct cpld_data {
        u8 cpld_ver_sub;        /* 0x1 - CPLD Minor Revision Register */
        u8 pcba_ver;            /* 0x2 - PCBA Revision Register */
        u8 system_rst;          /* 0x3 - system reset register */
-       u8 wd_cfg;              /* 0x4 - Watchdog Period Setting Register */
+       u8 res0;                /* 0x4 - not used */
        u8 sw_ctl_on;           /* 0x5 - Switch Control Enable Register */
        u8 por_cfg;             /* 0x6 - POR Control Register */
        u8 switch_strobe;       /* 0x7 - Multiplexed pin Select Register */
@@ -30,6 +27,7 @@ typedef struct cpld_data {
        u8 serdes_mux;          /* 0xc - Multiplexed pin Select Register */
        u8 sw[1];               /* 0xd - SW2 Status */
        u8 system_rst_default;  /* 0xe - system reset to default register */
+       u8 sysclk_sw1;          /* 0xf - sysclk configuration register */
 } __attribute__ ((packed)) cpld_data_t;
 
 #define SERDES_MUX_LANE_6_MASK 0x2
@@ -41,6 +39,8 @@ typedef struct cpld_data {
 #define SERDES_MUX_LANE_D_MASK 0x8
 #define SERDES_MUX_LANE_D_SHIFT        3
 #define CPLD_SWITCH_BANK_ENABLE        0x40
+#define CPLD_SYSCLK_83         0x1     /* system clock 83.3MHz */
+#define CPLD_SYSCLK_100                0x2     /* system clock 100MHz */
 
 /* Pointer to the CPLD register set */
 #define cpld ((cpld_data_t *)CPLD_BASE)