smdk5420: Remove GPIO enums

[u-boot] / board / freescale / t102xrdb / eth_t102xrdb.c

diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c
index 2e400c4ebf1e12f3dfc04a6c33e942f7d5d34c3a..f611ff07e98cb8858995f5d67c10257ea6b44c2b 100644 (file)
--- a/board/freescale/t102xrdb/eth_t102xrdb.c
+++ b/board/freescale/t102xrdb/eth_t102xrdb.c
@@ -21,6 +21,7 @@
 #include <phy.h>
 #include <asm/fsl_dtsec.h>
 #include <asm/fsl_serdes.h>
+#include "../common/fman.h"
 
 int board_eth_init(bd_t *bis)
 {
@@ -51,15 +52,22 @@ int board_eth_init(bd_t *bis)
        /* Register the 10G MDIO bus */
        fm_memac_mdio_init(bis, &tgec_mdio_info);
 
-       /* Set the two on-board RGMII PHY address */
-       fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
+       /* Set the on-board RGMII PHY address */
        fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
 
        switch (srds_s1) {
        case 0x95:
-               /* 10G XFI with Aquantia PHY */
+               /* set the on-board RGMII2  PHY */
+               fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
+
+               /* set 10G XFI with Aquantia AQR105 PHY */
                fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
                break;
+       case 0x77:
+       case 0x135:
+               /* set the on-board 2.5G SGMII AQR105 PHY */
+               fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY1_ADDR);
+               break;
        default:
                printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
                       srds_s1);
@@ -73,6 +81,10 @@ int board_eth_init(bd_t *bis)
                        dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
                        fm_info_set_mdio(i, dev);
                        break;
+               case PHY_INTERFACE_MODE_SGMII_2500:
+                       dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+                       fm_info_set_mdio(i, dev);
+                       break;
                default:
                        break;
                }
@@ -95,6 +107,18 @@ int board_eth_init(bd_t *bis)
        return pci_eth_init(bis);
 }
 
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+                             enum fm_port port, int offset)
+{
+       if ((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) &&
+           (port == FM1_DTSEC3)) {
+               fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
+               fdt_setprop(fdt, offset, "phy-connection-type",
+                           "sgmii-2500", 10);
+               fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
+       }
+}
+
 void fdt_fixup_board_enet(void *fdt)
 {
 }