powerpc/t4rdb: fix cpld reset altbank

[u-boot] / board / freescale / t104xrdb / spl.c

diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c
index 3822a377384df220301b5c6ad224c46633090b3f..4e8735b9ff19fb0112f799be3452657f54bf128b 100644 (file)
--- a/board/freescale/t104xrdb/spl.c
+++ b/board/freescale/t104xrdb/spl.c
@@ -11,7 +11,7 @@
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <spi_flash.h>
-#include <asm/mpc85xx_gpio.h>
+#include "../common/sleep.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -34,20 +34,26 @@ unsigned long get_board_ddr_clk(void)
 void board_init_f(ulong bootflag)
 {
        u32 plat_ratio, sys_clk, uart_clk;
-#ifdef CONFIG_SPL_NAND_BOOT
+#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
        u32 porsr1, pinctl;
+       u32 svr = get_svr();
 #endif
        ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
 
-#ifdef CONFIG_SPL_NAND_BOOT
-       /*
-        * There is T1040 SoC issue where NOR, FPGA are inaccessible during
-        * NAND boot because IFC signals > IFC_AD7 are not enabled.
-        * This workaround changes RCW source to make all signals enabled.
-        */
-       porsr1 = in_be32(&gur->porsr1);
-       pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
-       out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
+#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
+       if (IS_SVR_REV(svr, 1, 0)) {
+               /*
+                * There is T1040 SoC issue where NOR, FPGA are inaccessible
+                * during NAND boot because IFC signals > IFC_AD7 are not
+                * enabled. This workaround changes RCW source to make all
+                * signals enabled.
+                */
+               porsr1 = in_be32(&gur->porsr1);
+               pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK))
+                         | 0x24800000);
+               out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000),
+                        pinctl);
+       }
 #endif
 
        /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
@@ -58,8 +64,8 @@ void board_init_f(ulong bootflag)
 
 #ifdef CONFIG_DEEP_SLEEP
        /* disable the console if boot from deep sleep */
-       if (in_be32(&gur->scrtsr[0]) & (1 << 3))
-               gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+       if (is_warm_boot())
+               fsl_dp_disable_console();
 #endif
        /* compiler optimization barrier needed for GCC >= 3.4 */
        __asm__ __volatile__("" : : : "memory");
@@ -126,16 +132,3 @@ void board_init_r(gd_t *gd, ulong dest_addr)
        nand_boot();
 #endif
 }
-
-#ifdef CONFIG_DEEP_SLEEP
-void board_mem_sleep_setup(void)
-{
-       void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
-
-       /* does not provide HW signals for power management */
-       clrbits_8(cpld_base + 0x17, 0x40);
-       /* Disable MCKE isolation */
-       gpio_set_value(2, 0);
-       udelay(1);
-}
-#endif