Merge branch 'master' of git://git.denx.de/u-boot

[u-boot] / board / freescale / t4qds / t4240qds.c

diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c
index 7ee0f547866913edb03d56df021d308376a69525..fe1bc7f08df918eeb01ed0be831ab2ed91bab195 100644 (file)
--- a/board/freescale/t4qds/t4240qds.c
+++ b/board/freescale/t4qds/t4240qds.c
@@ -26,16 +26,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
+static int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
                                {8, 8}, {9, 9}, {14, 14}, {15, 15} };
 
-static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
+static int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
                                {10, 10}, {11, 11}, {12, 12}, {13, 13} };
 
-static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
+static int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
                                {10, 11}, {11, 10}, {12, 2}, {13, 3} };
 
-static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
+static int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
                                {8, 9}, {9, 8}, {14, 1}, {15, 0} };
 
 int checkboard(void)
@@ -353,25 +353,71 @@ int config_frontside_crossbar_vsc3316(void)
        srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
                        FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
        srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-       if (srds_prtcl_s1) {
+       switch (srds_prtcl_s1) {
+       case 37:
+       case 38:
+               /* swap first lane and third lane on slot1 */
+               vsc3316_fsm1_tx[0][1] = 14;
+               vsc3316_fsm1_tx[6][1] = 0;
+               vsc3316_fsm1_rx[1][1] = 2;
+               vsc3316_fsm1_rx[6][1] = 13;
+       case 39:
+       case 40:
+       case 45:
+       case 46:
+       case 47:
+       case 48:
+               /* swap first lane and third lane on slot2 */
+               vsc3316_fsm1_tx[2][1] = 8;
+               vsc3316_fsm1_tx[4][1] = 6;
+               vsc3316_fsm1_rx[2][1] = 10;
+               vsc3316_fsm1_rx[5][1] = 5;
+       default:
                ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
                if (ret)
                        return ret;
                ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
                if (ret)
                        return ret;
+               break;
        }
 
        srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
                                FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
        srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-       if (srds_prtcl_s2) {
+       switch (srds_prtcl_s2) {
+       case 37:
+       case 38:
+               /* swap first lane and third lane on slot3 */
+               vsc3316_fsm2_tx[2][1] = 11;
+               vsc3316_fsm2_tx[5][1] = 4;
+               vsc3316_fsm2_rx[2][1] = 9;
+               vsc3316_fsm2_rx[4][1] = 7;
+       case 39:
+       case 40:
+       case 45:
+       case 46:
+       case 47:
+       case 48:
+       case 49:
+       case 50:
+       case 51:
+       case 52:
+       case 53:
+       case 54:
+               /* swap first lane and third lane on slot4 */
+               vsc3316_fsm2_tx[6][1] = 3;
+               vsc3316_fsm2_tx[1][1] = 12;
+               vsc3316_fsm2_rx[0][1] = 1;
+               vsc3316_fsm2_rx[6][1] = 15;
+       default:
                ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
                if (ret)
                        return ret;
                ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
                if (ret)
                        return ret;
+               break;
        }
 
        return 0;
@@ -390,6 +436,7 @@ int config_backside_crossbar_mux(void)
        case 0:
                /* SerDes3 is not enabled */
                break;
+       case 1:
        case 2:
        case 9:
        case 10:
@@ -399,13 +446,20 @@ int config_backside_crossbar_mux(void)
                brdcfg |= BRDCFG12_SD3MX_SLOT5;
                QIXIS_WRITE(brdcfg[12], brdcfg);
                break;
+       case 3:
        case 4:
+       case 5:
        case 6:
+       case 7:
        case 8:
+       case 11:
        case 12:
+       case 13:
        case 14:
+       case 15:
        case 16:
        case 17:
+       case 18:
        case 19:
        case 20:
                /* SD3(4:7) => SLOT6(0:3) */
@@ -427,6 +481,7 @@ int config_backside_crossbar_mux(void)
        case 0:
                /* SerDes4 is not enabled */
                break;
+       case 1:
        case 2:
                /* 10b, SD4(0:7) => SLOT7(0:7) */
                brdcfg = QIXIS_READ(brdcfg[12]);
@@ -434,8 +489,11 @@ int config_backside_crossbar_mux(void)
                brdcfg |= BRDCFG12_SD4MX_SLOT7;
                QIXIS_WRITE(brdcfg[12], brdcfg);
                break;
+       case 3:
        case 4:
+       case 5:
        case 6:
+       case 7:
        case 8:
                /* x1b, SD4(4:7) => SLOT8(0:3) */
                brdcfg = QIXIS_READ(brdcfg[12]);
@@ -443,9 +501,13 @@ int config_backside_crossbar_mux(void)
                brdcfg |= BRDCFG12_SD4MX_SLOT8;
                QIXIS_WRITE(brdcfg[12], brdcfg);
                break;
+       case 9:
        case 10:
+       case 11:
        case 12:
+       case 13:
        case 14:
+       case 15:
        case 16:
        case 18:
                /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */
@@ -573,22 +635,6 @@ unsigned long get_board_ddr_clk(void)
        return 66666666;
 }
 
-static const char *serdes_clock_to_string(u32 clock)
-{
-       switch (clock) {
-       case SRDS_PLLCR0_RFCK_SEL_100:
-               return "100";
-       case SRDS_PLLCR0_RFCK_SEL_125:
-               return "125";
-       case SRDS_PLLCR0_RFCK_SEL_156_25:
-               return "156.25";
-       case SRDS_PLLCR0_RFCK_SEL_161_13:
-               return "161.1328125";
-       default:
-               return "???";
-       }
-}
-
 int misc_init_r(void)
 {
        u8 sw;