imx6ul: geam: Fix fdt_file mismatch

[u-boot] / board / freescale / t4rdb / t4240rdb.c

diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c
index 5448c86c48237150dcfcb8ff7109f1bd9a9bda7e..3bfebb62147cdc9706261ae998ae56d7cfc54f70 100644 (file)
--- a/board/freescale/t4rdb/t4240rdb.c
+++ b/board/freescale/t4rdb/t4240rdb.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
  */
 
 #include <common.h>
@@ -15,19 +14,31 @@
 #include <asm/immap_85xx.h>
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
 #include <asm/fsl_liodn.h>
 #include <fm_eth.h>
 
 #include "t4rdb.h"
+#include "cpld.h"
+#include "../common/vid.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
 int checkboard(void)
 {
        struct cpu_type *cpu = gd->arch.cpu;
+       u8 sw;
 
        printf("Board: %sRDB, ", cpu->name);
+       printf("Board rev: 0x%02x CPLD ver: 0x%02x%02x, ",
+              CPLD_READ(hw_ver), CPLD_READ(sw_maj_ver), CPLD_READ(sw_min_ver));
+
+       sw = CPLD_READ(vbank);
+       sw = sw & CPLD_BANK_SEL_MASK;
+
+       if (sw <= 7)
+               printf("vBank: %d\n", sw);
+       else
+               printf("Unsupported Bank=%x\n", sw);
 
        puts("SERDES Reference Clocks:\n");
        printf("       SERDES1=100MHz SERDES2=156.25MHz\n"
@@ -39,7 +50,7 @@ int checkboard(void)
 int board_early_init_r(void)
 {
        const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
-       const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+       int flash_esel = find_tlb_idx((void *)flashbase, 1);
 
        /*
         * Remap Boot flash + PROMJET region to caching-inhibited
@@ -50,17 +61,25 @@ int board_early_init_r(void)
        flush_dcache();
        invalidate_icache();
 
-       /* invalidate existing TLB entry for flash + promjet */
-       disable_tlb(flash_esel);
+       if (flash_esel == -1) {
+               /* very unlikely unless something is messed up */
+               puts("Error: Could not find TLB for FLASH BASE\n");
+               flash_esel = 2; /* give our best effort to continue */
+       } else {
+               /* invalidate existing TLB entry for flash + promjet */
+               disable_tlb(flash_esel);
+       }
 
        set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
                MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                0, flash_esel, BOOKE_PAGESZ_256M, 1);
 
-       set_liodns();
-#ifdef CONFIG_SYS_DPAA_QBMAN
-       setup_portals();
-#endif
+       /*
+        * Adjust core voltage according to voltage ID
+        * This function changes I2C mux to channel 2.
+       */
+       if (adjust_vdd(0))
+               printf("Warning: Adjusting core voltage failed.\n");
 
        return 0;
 }
@@ -70,15 +89,15 @@ int misc_init_r(void)
        return 0;
 }
 
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
 {
        phys_addr_t base;
        phys_size_t size;
 
        ft_cpu_setup(blob, bd);
 
-       base = getenv_bootm_low();
-       size = getenv_bootm_size();
+       base = env_get_bootm_low();
+       size = env_get_bootm_size();
 
        fdt_fixup_memory(blob, (u64)base, (u64)size);
 
@@ -87,12 +106,14 @@ void ft_board_setup(void *blob, bd_t *bd)
 #endif
 
        fdt_fixup_liodn(blob);
-       fdt_fixup_dr_usb(blob, bd);
+       fsl_fdt_fixup_dr_usb(blob, bd);
 
 #ifdef CONFIG_SYS_DPAA_FMAN
        fdt_fixup_fman_ethernet(blob);
        fdt_fixup_board_enet(blob);
 #endif
+
+       return 0;
 }
 
 /*