]> git.sur5r.net Git - u-boot/blobdiff - board/gdsys/405ep/dlvision-10g.c
iocon: reset FPGAs in last_stage_init()
[u-boot] / board / gdsys / 405ep / dlvision-10g.c
index adaffb26d7fe5f57af3943f75bfd2339a77d1e4d..54c7eb3a12aba1abbf3f33e7dc0b6fb420ad3451 100644 (file)
@@ -2,23 +2,7 @@
  * (C) Copyright 2010
  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -26,6 +10,7 @@
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <asm/ppc4xx-gpio.h>
+#include <dtt.h>
 
 #include "405ep.h"
 #include <gdsys_fpga.h>
 #define LATCH2_MC2_PRESENT_N 0x0080
 
 enum {
-       UNITTYPE_VIDEO_USER = 0,
-       UNITTYPE_MAIN_USER = 1,
-       UNITTYPE_VIDEO_SERVER = 2,
-       UNITTYPE_MAIN_SERVER = 3,
+       UNITTYPE_MAIN = 1<<0,
+       UNITTYPE_SERVER = 1<<1,
+       UNITTYPE_DISPLAYPORT = 1<<2,
 };
 
 enum {
        HWVER_101 = 0,
        HWVER_110 = 1,
+       HWVER_130 = 2,
+       HWVER_140 = 3,
+       HWVER_150 = 4,
+       HWVER_160 = 5,
+       HWVER_170 = 6,
 };
 
 enum {
@@ -68,6 +57,16 @@ enum {
        RAM_DDR2_64 = 2,
 };
 
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
+int misc_init_r(void)
+{
+       /* startup fans */
+       dtt_init();
+
+       return 0;
+}
+
 static unsigned int get_hwver(void)
 {
        u16 latch3 = in_le16((void *)LATCH3_BASE);
@@ -84,10 +83,9 @@ static unsigned int get_mc2_present(void)
 
 static void print_fpga_info(unsigned dev)
 {
-       ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
-       u16 versions = in_le16(&fpga->versions);
-       u16 fpga_version = in_le16(&fpga->fpga_version);
-       u16 fpga_features = in_le16(&fpga->fpga_features);
+       u16 versions;
+       u16 fpga_version;
+       u16 fpga_features;
        unsigned unit_type;
        unsigned hardware_version;
        unsigned feature_rs232;
@@ -101,6 +99,10 @@ static void print_fpga_info(unsigned dev)
 
        printf("FPGA%d: ", dev);
 
+       FPGA_GET_REG(dev, versions, &versions);
+       FPGA_GET_REG(dev, fpga_version, &fpga_version);
+       FPGA_GET_REG(dev, fpga_features, &fpga_features);
+
        hardware_version = versions & 0x000f;
 
        if (fpga_state
@@ -121,35 +123,48 @@ static void print_fpga_info(unsigned dev)
        feature_carriers = (fpga_features >> 2) & 0x0003;
        feature_video_channels = fpga_features & 0x0003;
 
-       switch (unit_type) {
-       case UNITTYPE_VIDEO_USER:
-               printf("Videochannel Userside");
+       if (unit_type & UNITTYPE_MAIN)
+               printf("Mainchannel ");
+       else
+               printf("Videochannel ");
+
+       if (unit_type & UNITTYPE_SERVER)
+               printf("Serverside ");
+       else
+               printf("Userside ");
+
+       if (unit_type & UNITTYPE_DISPLAYPORT)
+               printf("DisplayPort");
+       else
+               printf("DVI-DL");
+
+       switch (hardware_version) {
+       case HWVER_101:
+               printf(" HW-Ver 1.01\n");
                break;
 
-       case UNITTYPE_MAIN_USER:
-               printf("Mainchannel Userside");
+       case HWVER_110:
+               printf(" HW-Ver 1.10-1.20\n");
                break;
 
-       case UNITTYPE_VIDEO_SERVER:
-               printf("Videochannel Serverside");
+       case HWVER_130:
+               printf(" HW-Ver 1.30\n");
                break;
 
-       case UNITTYPE_MAIN_SERVER:
-               printf("Mainchannel Serverside");
+       case HWVER_140:
+               printf(" HW-Ver 1.40-1.43\n");
                break;
 
-       default:
-               printf("UnitType %d(not supported)", unit_type);
+       case HWVER_150:
+               printf(" HW-Ver 1.50\n");
                break;
-       }
 
-       switch (hardware_version) {
-       case HWVER_101:
-               printf(" HW-Ver 1.01\n");
+       case HWVER_160:
+               printf(" HW-Ver 1.60-1.61\n");
                break;
 
-       case HWVER_110:
-               printf(" HW-Ver 1.10\n");
+       case HWVER_170:
+               printf(" HW-Ver 1.70\n");
                break;
 
        default:
@@ -226,33 +241,33 @@ static void print_fpga_info(unsigned dev)
  */
 int checkboard(void)
 {
-       char buf[64];
-       int i = getenv_f("serial#", buf, sizeof(buf));
+       char *s = getenv("serial#");
 
-       printf("Board: ");
+       puts("Board: ");
 
-       printf("DLVision 10G");
+       puts("DLVision 10G");
 
-       if (i > 0) {
+       if (s != NULL) {
                puts(", serial# ");
-               puts(buf);
+               puts(s);
        }
 
        puts("\n");
 
-       print_fpga_info(0);
-       if (get_mc2_present())
-               print_fpga_info(1);
-
        return 0;
 }
 
 int last_stage_init(void)
 {
-       ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
-       u16 versions = in_le16(&fpga->versions);
+       u16 versions;
+
+       FPGA_GET_REG(0, versions, &versions);
+
+       print_fpga_info(0);
+       if (get_mc2_present())
+               print_fpga_info(1);
 
-       if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER)
+       if (((versions >> 4) & 0x000f) & UNITTYPE_SERVER)
                return 0;
 
        if (!get_fpga_state(0) || (get_hwver() == HWVER_101))