Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze

[u-boot] / board / gdsys / 405ex / 405ex.c

diff --git a/board/gdsys/405ex/405ex.c b/board/gdsys/405ex/405ex.c
index 32e24c08cb9ce8340f589ab21d1772ef61bea087..9e1c57f80857167c455dfafc90e926dbc16a1dc2 100644 (file)
--- a/board/gdsys/405ex/405ex.c
+++ b/board/gdsys/405ex/405ex.c
@@ -11,6 +11,12 @@
 #define REFLECTION_TESTPATTERN 0xdede
 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
 
+#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
+#define REFLECTION_TESTREG reflection_low
+#else
+#define REFLECTION_TESTREG reflection_high
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 int get_fpga_state(unsigned dev)
@@ -18,14 +24,6 @@ int get_fpga_state(unsigned dev)
        return gd->arch.fpga_state[dev];
 }
 
-void print_fpga_state(unsigned dev)
-{
-       if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
-               puts("       Waiting for FPGA-DONE timed out.\n");
-       if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
-               puts("       FPGA reflection test failed.\n");
-}
-
 int board_early_init_f(void)
 {
        u32 val;
@@ -220,23 +218,17 @@ int board_early_init_r(void)
        gd405ex_set_fpga_reset(0);
 
        for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
-               struct ihs_fpga *fpga =
-                       (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k);
-#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
-               u16 *reflection_target = &fpga->reflection_low;
-#else
-               u16 *reflection_target = &fpga->reflection_high;
-#endif
                /*
                 * wait for fpga out of reset
                 */
                ctr = 0;
                while (1) {
-                       out_le16(&fpga->reflection_low,
-                               REFLECTION_TESTPATTERN);
+                       u16 val;
+
+                       FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
 
-                       if (in_le16(reflection_target) ==
-                               REFLECTION_TESTPATTERN_INV)
+                       FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
+                       if (val == REFLECTION_TESTPATTERN_INV)
                                break;
 
                        udelay(100000);