]> git.sur5r.net Git - u-boot/blobdiff - board/gdsys/p1022/controlcenterd.c
env: Rename some other getenv()-related functions
[u-boot] / board / gdsys / p1022 / controlcenterd.c
index 8ccd9ce6baa2c9e7e080d01cd9a2da47c0aa69df..9fb814d8c7c0de99fc4de43bcab5e20073f81778 100644 (file)
@@ -57,6 +57,8 @@ struct ihs_fpga {
        u32 versions;           /* 0x0004 */
        u32 fpga_version;       /* 0x0008 */
        u32 fpga_features;      /* 0x000c */
+       u32 reserved[4];        /* 0x0010 */
+       u32 control;            /* 0x0020 */
 };
 
 #ifndef CONFIG_TRAILBLAZER
@@ -221,11 +223,7 @@ void hw_watchdog_reset(void)
 #ifdef CONFIG_TRAILBLAZER
 int do_bootd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-       int rcode = 0;
-
-       if (run_command(getenv("bootcmd"), flag) < 0)
-               rcode = 1;
-       return rcode;
+       return run_command(env_get("bootcmd"), flag);
 }
 
 int board_early_init_r(void)
@@ -330,23 +328,25 @@ int board_eth_init(bd_t *bis)
 }
 
 #ifdef CONFIG_OF_BOARD_SETUP
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
 {
        phys_addr_t base;
        phys_size_t size;
 
        ft_cpu_setup(blob, bd);
 
-       base = getenv_bootm_low();
-       size = getenv_bootm_size();
+       base = env_get_bootm_low();
+       size = env_get_bootm_size();
 
        fdt_fixup_memory(blob, (u64)base, (u64)size);
 
 #ifdef CONFIG_HAS_FSL_DR_USB
-       fdt_fixup_dr_usb(blob, bd);
+       fsl_fdt_fixup_dr_usb(blob, bd);
 #endif
 
        FT_FSL_PCI_SETUP;
+
+       return 0;
 }
 #endif
 
@@ -386,9 +386,12 @@ static void hydra_initialize(void)
                fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
                        PCI_REGION_MEM);
 
-               versions = readl(fpga->versions);
-               fpga_version = readl(fpga->fpga_version);
-               fpga_features = readl(fpga->fpga_features);
+               /* disable sideband clocks */
+               writel(1, &fpga->control);
+
+               versions = readl(&fpga->versions);
+               fpga_version = readl(&fpga->fpga_version);
+               fpga_features = readl(&fpga->fpga_features);
 
                hardware_version = versions & 0xf;
                feature_uart_channels = (fpga_features >> 6) & 0x1f;