Merge branch 'master' of git://git.denx.de/u-boot-atmel

[u-boot] / board / imgtec / malta / malta.c

diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
index d363e49919e96454e692658289271b448c29f64f..e31331aec1ecaacb8e69d0eba3fce2312dcdb832 100644 (file)
--- a/board/imgtec/malta/malta.c
+++ b/board/imgtec/malta/malta.c
@@ -6,6 +6,7 @@
  */
 
 #include <common.h>
+#include <ide.h>
 #include <netdev.h>
 #include <pci.h>
 #include <pci_gt64120.h>
@@ -37,7 +38,7 @@ static void malta_lcd_puts(const char *str)
        void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0);
 
        /* print up to 8 characters of the string */
-       for (i = 0; i < min(strlen(str), 8); i++) {
+       for (i = 0; i < min((int)strlen(str), 8); i++) {
                __raw_writel(str[i], reg);
                reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
        }
@@ -52,8 +53,9 @@ static void malta_lcd_puts(const char *str)
 static enum core_card malta_core_card(void)
 {
        u32 corid, rev;
+       const void *reg = (const void *)CKSEG1ADDR(MALTA_REVISION);
 
-       rev = __raw_readl(CKSEG1ADDR(MALTA_REVISION));
+       rev = __raw_readl(reg);
        corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF;
 
        switch (corid) {
@@ -123,28 +125,31 @@ void _machine_restart(void)
 
        reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
        __raw_writel(GORESET, reset_base);
+       mdelay(1000);
 }
 
 int board_early_init_f(void)
 {
-       void *io_base;
+       ulong io_base;
 
        /* choose correct PCI I/O base */
        switch (malta_sys_con()) {
        case SYSCON_GT64120:
-               io_base = (void *)CKSEG1ADDR(MALTA_GT_PCIIO_BASE);
+               io_base = CKSEG1ADDR(MALTA_GT_PCIIO_BASE);
                break;
 
        case SYSCON_MSC01:
-               io_base = (void *)CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE);
+               io_base = CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE);
                break;
 
        default:
                return -1;
        }
 
+       set_io_port_base(io_base);
+
        /* setup FDC37M817 super I/O controller */
-       malta_superio_init(io_base);
+       malta_superio_init();
 
        return 0;
 }
@@ -176,8 +181,6 @@ void pci_init_board(void)
 
        switch (malta_sys_con()) {
        case SYSCON_GT64120:
-               set_io_port_base(CKSEG1ADDR(MALTA_GT_PCIIO_BASE));
-
                gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
                                 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
                                 0x10000000, 0x10000000, 128 * 1024 * 1024,
@@ -186,8 +189,6 @@ void pci_init_board(void)
 
        default:
        case SYSCON_MSC01:
-               set_io_port_base(CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE));
-
                msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE),
                               0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
                               MALTA_MSC01_PCIMEM_MAP,
@@ -217,4 +218,22 @@ void pci_init_board(void)
        pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8);
        val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT;
        pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8);
+
+       bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
+                             PCI_DEVICE_ID_INTEL_82371AB, 0);
+       if (bdf == -1)
+               panic("Failed to find PIIX4 IDE controller\n");
+
+       /* enable bus master & IO access */
+       val32 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
+       pci_write_config_dword(bdf, PCI_COMMAND, val32);
+
+       /* set latency */
+       pci_write_config_byte(bdf, PCI_LATENCY_TIMER, 0x40);
+
+       /* enable IDE/ATA */
+       pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_PRI,
+                              PCI_CFG_PIIX4_IDETIM_IDE);
+       pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC,
+                              PCI_CFG_PIIX4_IDETIM_IDE);
 }