REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
- REG CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \
- PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | \
- PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | \
- PDR0_MCU_PODF(0)
+ REG CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)
- REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | \
- PLL_MFN(0x23)
+ REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)
REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
REG 0x43FAC26C, 0 /* SDCLK */
REG 0x43FAC270, 0 /* CAS */
REG 0x43FAC274, 0 /* RAS */
- REG 0x43FAC27C, 0x1000 /* CS2 CSD0) */
+ REG 0x43FAC27C, 0x1000 /* CS2 (CSD0) */
REG 0x43FAC284, 0 /* DQM3 */
- /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 0x288..0x2DC) */
- REG 0x43FAC288, 0
+ REG 0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
REG 0x43FAC28C, 0
REG 0x43FAC290, 0
REG 0x43FAC294, 0
REG 0xB8001000, 0xb2100000
REG8 0x80000033, 0xda
REG8 0x81000000, 0xff
+ REG 0xB8001000, 0x82226080
+ REG 0x80000000, 0xDEADBEEF
+ REG 0xB8001010, 0x0000000c
+
+ mov pc, lr