Merge branch 'next' of git://git.denx.de/u-boot-mpc83xx

[u-boot] / board / imx31_phycore / lowlevel_init.S

diff --git a/board/imx31_phycore/lowlevel_init.S b/board/imx31_phycore/lowlevel_init.S
index b0a5389181eadc117dea524ff44e1af92594ee34..6ea3878ef9c466658b7f1b4a8908cc301b60b42b 100644 (file)
--- a/board/imx31_phycore/lowlevel_init.S
+++ b/board/imx31_phycore/lowlevel_init.S
@@ -2,26 +2,10 @@
  *
  * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/imx-regs.h>
 
 .macro REG reg, val
        ldr r2, =\reg
@@ -54,10 +38,7 @@ lowlevel_init:
        REG     CCM_CCMR, 0x074B0BF5 | CCMR_MPE
        REG     CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
 
-       REG     CCM_PDR0, PDR0_CSI_PODF(0xff1) | PDR0_PER_PODF(7) |     \
-                       PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |           \
-                       PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |           \
-                       PDR0_MCU_PODF(0)
+       REG     CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)
 
        REG     CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd)
 
@@ -66,10 +47,9 @@ lowlevel_init:
        REG     0x43FAC26C, 0 /* SDCLK */
        REG     0x43FAC270, 0 /* CAS */
        REG     0x43FAC274, 0 /* RAS */
-       REG     0x43FAC27C, 0x1000 /* CS2       CSD0) */
+       REG     0x43FAC27C, 0x1000 /* CS2 (CSD0) */
        REG     0x43FAC284, 0 /* DQM3 */
-               /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 0x288..0x2DC) */
-       REG     0x43FAC288, 0
+       REG     0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
        REG     0x43FAC28C, 0
        REG     0x43FAC290, 0
        REG     0x43FAC294, 0
@@ -103,3 +83,6 @@ lowlevel_init:
        REG8    0x81000000, 0xff
        REG     0xB8001000, 0x82226080
        REG     0x80000000, 0xDEADBEEF
+       REG     0xB8001010, 0x0000000c
+
+       mov     pc, lr