#include <libfdt.h>
#endif
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
#include <i2c.h>
-#endif
-
#include "../common/common.h"
/*
return size;
}
+#ifdef CONFIG_SYS_SDRAM_LIST
+
+/*
+ * If CONFIG_SYS_SDRAM_LIST is defined, we cycle through all SDRAM
+ * configurations therein (should be from high to lower) to find the
+ * one actually matching the current configuration.
+ * CONFIG_SYS_PSDMR and CONFIG_SYS_OR1 will contain the base values which are
+ * common among all possible configurations; values in CONFIG_SYS_SDRAM_LIST
+ * (defined as the initialization value for the array of struct sdram_conf_s)
+ * will then be ORed with such base values.
+ */
+
+struct sdram_conf_s {
+ ulong size;
+ int or1;
+ int psdmr;
+};
+
+static struct sdram_conf_s sdram_conf[] = CONFIG_SYS_SDRAM_LIST;
+
+static long probe_sdram(memctl8260_t *memctl)
+{
+ int n = 0;
+ long psize = 0;
+
+ for (n = 0; n < ARRAY_SIZE(sdram_conf); psize = 0, n++) {
+ psize = try_init(memctl,
+ CONFIG_SYS_PSDMR | sdram_conf[n].psdmr,
+ CONFIG_SYS_OR1 | sdram_conf[n].or1,
+ (uchar *) CONFIG_SYS_SDRAM_BASE);
+ debug("Probing %ld bytes returned %ld\n",
+ sdram_conf[n].size, psize);
+ if (psize == sdram_conf[n].size)
+ break;
+ }
+ return psize;
+}
+
+#else /* CONFIG_SYS_SDRAM_LIST */
+
+static long probe_sdram(memctl8260_t *memctl)
+{
+ return try_init(memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1,
+ (uchar *) CONFIG_SYS_SDRAM_BASE);
+}
+#endif /* CONFIG_SYS_SDRAM_LIST */
+
+
phys_size_t initdram(int board_type)
{
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
#ifndef CONFIG_SYS_RAMBOOT
/* 60x SDRAM setup:
*/
- psize = try_init(memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
+ psize = probe_sdram(memctl);
#endif /* CONFIG_SYS_RAMBOOT */
icache_enable();
#if defined(CONFIG_MGCOGE)
puts("Board: Keymile mgcoge");
#else
- puts("Board: Keymile mgcoge2ne");
+ puts("Board: Keymile mgcoge3ne");
#endif
if (ethernet_present())
puts(" with PIGGY.");
return 0;
}
-#define DIPSWITCH_OFFSET 0x89
-#define DIPSWITCH_MASK 0x0f
-
int last_stage_init(void)
{
+ struct bfticu_iomap *base =
+ (struct bfticu_iomap *)CONFIG_SYS_FPGA_BASE;
u8 dip_switch;
- /* Dip switch */
- dip_switch = readb(CONFIG_SYS_BFTICU_BASE + DIPSWITCH_OFFSET);
- dip_switch &= DIPSWITCH_MASK;
+
+ dip_switch = in_8(&base->mswitch);
+ dip_switch &= BFTICU_DIPSWITCH_MASK;
/* dip switch 'full reset' or 'db erase' */
if (dip_switch & 0x1 || dip_switch & 0x2) {
/* start bootloader */
return 0;
}
+#ifdef CONFIG_MGCOGE3NE
+static void set_pin(int state, unsigned long mask);
+
+/*
+ * For mgcoge3ne boards, the mgcoge3un control is controlled from
+ * a GPIO line on the PPC CPU. If bobcatreset is set the line
+ * will toggle once what forces the mgocge3un part to restart
+ * immediately.
+ */
+static void handle_mgcoge3un_reset(void)
+{
+ char *bobcatreset = getenv("bobcatreset");
+ if (bobcatreset) {
+ if (strcmp(bobcatreset, "true") == 0) {
+ puts("Forcing bobcat reset\n");
+ set_pin(0, 0x00000004); /* clear PD29 to reset arm */
+ udelay(1000);
+ set_pin(1, 0x00000004);
+ } else
+ set_pin(1, 0x00000004); /* set PD29 to not reset arm */
+ }
+}
+#endif
+
+int ethernet_present(void)
+{
+ struct km_bec_fpga *base =
+ (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
+
+ return in_8(&base->bprth) & PIGGY_PRESENT;
+}
+
/*
* Early board initalization.
*/
out_8(&base->oprtl, (H_OPORTS_SCC4_ENA | H_OPORTS_SCC4_FD_ENA |
H_OPORTS_FCC1_PW_DWN));
+#ifdef CONFIG_MGCOGE3NE
+ handle_mgcoge3un_reset();
+#endif
return 0;
}
return 0;
}
+#define SDA_MASK 0x00010000
+#define SCL_MASK 0x00020000
+
+static void set_pin(int state, unsigned long mask)
+{
+ ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
+
+ if (state)
+ setbits_be32(&iop->pdat, mask);
+ else
+ clrbits_be32(&iop->pdat, mask);
+
+ setbits_be32(&iop->pdir, mask);
+}
+
+static int get_pin(unsigned long mask)
+{
+ ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
+
+ clrbits_be32(&iop->pdir, mask);
+ return 0 != (in_be32(&iop->pdat) & mask);
+}
+
+void set_sda(int state)
+{
+ set_pin(state, SDA_MASK);
+}
+
+void set_scl(int state)
+{
+ set_pin(state, SCL_MASK);
+}
+
+int get_sda(void)
+{
+ return get_pin(SDA_MASK);
+}
+
+int get_scl(void)
+{
+ return get_pin(SCL_MASK);
+}
+
+#if defined(CONFIG_HARD_I2C)
+static void setports(int gpio)
+{
+ ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
+
+ if (gpio) {
+ clrbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
+ clrbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
+ } else {
+ setbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
+ clrbits_be32(&iop->pdir, (SDA_MASK | SCL_MASK));
+ setbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
+ }
+}
+#endif
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
void ft_board_setup(void *blob, bd_t *bd)
{
projects / u-boot / blobdiff