powerpc/82xx: add SDRAM detection for km82xx

[u-boot] / board / keymile / km_arm / km_arm.c

diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 831cbd98dc06209cff9f2bfe12ef4cb6570057bc..2b2ca393765818a2dc2898d159140834560d3ac8 100644 (file)
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -243,45 +243,79 @@ int misc_init_r(void)
 
 int board_early_init_f(void)
 {
+#if defined(CONFIG_SOFT_I2C)
        u32 tmp;
 
+       /* set the 2 bitbang i2c pins as output gpios */
+       tmp = readl(KW_GPIO0_BASE + 4);
+       writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4);
+#endif
+
        kirkwood_mpp_conf(kwmpp_config, NULL);
+       return 0;
+}
+
+int board_init(void)
+{
+       /*
+        * arch number of board
+        */
+       gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD;
+
+       /* address of boot parameters */
+       gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
 
        /*
-        * The FLASH_GPIO_PIN switches between using a
+        * The KM_FLASH_GPIO_PIN switches between using a
         * NAND or a SPI FLASH. Set this pin on start
         * to NAND mode.
         */
-       tmp = readl(KW_GPIO0_BASE);
-       writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
-       tmp = readl(KW_GPIO0_BASE + 4);
-       writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
+       kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
+       kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
 
 #if defined(CONFIG_SOFT_I2C)
-       /* init the GPIO for I2C Bitbang driver */
+       /*
+        * Reinit the GPIO for I2C Bitbang driver so that the now
+        * available gpio framework is consistent. The calls to
+        * direction output in are not necessary, they are already done in
+        * board_early_init_f
+        */
        kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
        kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
-       kw_gpio_direction_output(KM_KIRKWOOD_SDA_PIN, 0);
-       kw_gpio_direction_output(KM_KIRKWOOD_SCL_PIN, 0);
 #endif
+
 #if defined(CONFIG_SYS_EEPROM_WREN)
        kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
        kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
 #endif
-#if defined(CONFIG_KM_RECONFIG_XLX)
-       /* trigger the reconfiguration of the xilinx fpga */
-       kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1);
-       kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0);
-       kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN);
+
+#if defined(CONFIG_KM_FPGA_CONFIG)
+       trigger_fpga_config();
 #endif
+
        return 0;
 }
 
-int board_init(void)
+int board_late_init(void)
 {
-       /* address of boot parameters */
-       gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+#if defined(CONFIG_KMCOGE5UN)
+/* I/O pin to erase flash RGPP09 = MPP43 */
+#define KM_FLASH_ERASE_ENABLE  43
+       u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
+
+       /* if pin 1 do full erase */
+       if (dip_switch != 0) {
+               /* start bootloader */
+               puts("DIP:   Enabled\n");
+               setenv("actual_bank", "0");
+       }
+#endif
 
+#if defined(CONFIG_KM_FPGA_CONFIG)
+       wait_for_fpga_config();
+       fpga_reset();
+       toggle_eeprom_spi_bus();
+#endif
        return 0;
 }
 
@@ -317,15 +351,15 @@ void dram_init_banksize(void)
        }
 }
 
-#if (defined(CONFIG_KM_MGCOGE3UN)|defined(CONFIG_PORTL2))
+#if (defined(CONFIG_KM_PIGGY4_88E6061))
 
-#define        PHY_LED_SEL     0x18
-#define PHY_LED0_LINK  (0x5)
-#define PHY_LED1_ACT   (0x8<<4)
-#define PHY_LED2_INT   (0xe<<8)
-#define        PHY_SPEC_CTRL   0x1c
+#define        PHY_LED_SEL_REG         0x18
+#define PHY_LED0_LINK          (0x5)
+#define PHY_LED1_ACT           (0x8<<4)
+#define PHY_LED2_INT           (0xe<<8)
+#define        PHY_SPEC_CTRL_REG       0x1c
 #define PHY_RGMII_CLK_STABLE   (0x1<<10)
-#define PHY_CLSA       (0x1<<1)
+#define PHY_CLSA               (0x1<<1)
 
 /* Configure and enable MV88E3018 PHY */
 void reset_phy(void)
@@ -337,15 +371,15 @@ void reset_phy(void)
                return;
 
        /* RGMII clk transition on data stable */
-       if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, &reg) != 0)
+       if (!miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, &reg))
                printf("Error reading PHY spec ctrl reg\n");
-       if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL,
-               reg | PHY_RGMII_CLK_STABLE | PHY_CLSA) != 0)
+       if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
+               reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
                printf("Error writing PHY spec ctrl reg\n");
 
        /* leds setup */
-       if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL,
-               PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT) != 0)
+       if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
+               PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
                printf("Error writing PHY LED reg\n");
 
        /* reset the phy */