]> git.sur5r.net Git - u-boot/blobdiff - board/linkstation/ide.c
cmd_mmc remove \n
[u-boot] / board / linkstation / ide.c
index 37d9b57fad30d9290a601113bfccace0ed3b4b94..568fdf5f2e8ce7b2c06f98ddca4c03bcb0ee0dd5 100644 (file)
@@ -37,7 +37,7 @@
 #define IT8212_PCI_IdeBusSkewCONTROL   0x4c
 #define IT8212_PCI_IdeDrivingCURRENT   0x42
 
-extern ulong ide_bus_offset[CFG_IDE_MAXBUS];
+extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];
 extern struct pci_controller hose;
 
 int ide_preinit (void)
@@ -47,18 +47,20 @@ int ide_preinit (void)
        int l;
 
        status = 1;
-       for (l = 0; l < CFG_IDE_MAXBUS; l++) {
+       for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) {
                ide_bus_offset[l] = -ATA_STATUS;
        }
        devbusfn = pci_find_device(PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680, 0);
        if (devbusfn == -1)
                devbusfn = pci_find_device(PCI_VENDOR_ID_ITE,PCI_DEVICE_ID_ITE_8212,0);
        if (devbusfn != -1) {
+               u32 ide_bus_offset32;
+
                status = 0;
 
                pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
-                                                          (u32 *) &ide_bus_offset[0]);
-               ide_bus_offset[0] &= 0xfffffffe;
+                                                          &ide_bus_offset32);
+               ide_bus_offset[0] = ide_bus_offset32 & 0xfffffffe;
                ide_bus_offset[0] = pci_hose_bus_to_phys(&hose,
                                                         ide_bus_offset[0] & 0xfffffffe,
                                                         PCI_REGION_IO);
@@ -81,12 +83,12 @@ int ide_preinit (void)
 #endif
                pci_write_config_dword(devbusfn, IT8212_PCI_IdeBusSkewCONTROL, 0x02040204);
 /* __LS_COMMENT__ BUFFALO changed 2004.11.10  changed for EMI */
-        pci_write_config_byte(devbusfn, IT8212_PCI_IdeDrivingCURRENT, 0x36); /* 10mA */
-/*      pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x09); */ /* 4mA */
-/*      pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x12); */ /* 6mA */
-/*      pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x24); */ /* 6mA,2mA */
-/*      pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x2D); */ /* 8mA,4mA */
-        pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x00);
+               pci_write_config_byte(devbusfn, IT8212_PCI_IdeDrivingCURRENT, 0x36); /* 10mA */
+/*             pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x09); */ /* 4mA */
+/*             pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x12); */ /* 6mA */
+/*             pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x24); */ /* 6mA,2mA */
+/*             pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x2D); */ /* 8mA,4mA */
+               pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x00);
        }
 
        return (status);