ARM: omap3_logic: Enable SPL_OF_CONTROL and SPL_OF_PLATDATA

[u-boot] / board / logicpd / omap3som / omap3logic.c

diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
index a55a520e63e512a69f237599b6311766feb69078..4cbbf96faa393cbcb7f842fced8815c5ffa3ee4b 100644 (file)
--- a/board/logicpd/omap3som/omap3logic.c
+++ b/board/logicpd/omap3som/omap3logic.c
@@ -40,21 +40,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/* This is only needed until SPL gets OF support */
-#ifdef CONFIG_SPL_BUILD
-static const struct ns16550_platdata omap3logic_serial = {
-       .base = OMAP34XX_UART1,
-       .reg_shift = 2,
-       .clock = V_NS16550_CLK,
-       .fcr = UART_FCR_DEFVAL,
-};
-
-U_BOOT_DEVICE(omap3logic_uart) = {
-       "ns16550_serial",
-       &omap3logic_serial
-};
-#endif
-
 /*
  * two dimensional array of strucures containining board name and Linux
  * machine IDs; row it selected based on CPU column is slected based
@@ -114,6 +99,47 @@ void get_board_mem_timings(struct board_sdrc_timings *timings)
        timings->ctrlb = MICRON_V_ACTIMB_200;
        timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
 }
+
+#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c)
+#define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE + 0x84)
+#define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE + 0x80)
+
+void spl_board_prepare_for_linux(void)
+{
+       /* The Micron NAND starts locked which
+        * prohibits mounting the NAND as RW
+        * The following commands are what unlocks
+        * the NAND to become RW Falcon Mode does not
+        * have as many smarts as U-Boot, but Logic PD
+        * only makes NAND with 512MB so these hard coded
+        * values should work for all current models
+        */
+
+       writeb(0x70, GPMC_NAND_COMMAND_0);
+       writeb(-1, GPMC_NAND_DATA_0);
+       writeb(0x7a, GPMC_NAND_COMMAND_0);
+       writeb(0x00, GPMC_NAND_ADDRESS_0);
+       writeb(0x00, GPMC_NAND_ADDRESS_0);
+       writeb(0x00, GPMC_NAND_ADDRESS_0);
+       writeb(-1, GPMC_NAND_COMMAND_0);
+
+       /* Begin address 0 */
+       writeb(NAND_CMD_UNLOCK1, 0x6e00007c);
+       writeb(0x00, GPMC_NAND_ADDRESS_0);
+       writeb(0x00, GPMC_NAND_ADDRESS_0);
+       writeb(0x00, GPMC_NAND_ADDRESS_0);
+       writeb(-1, GPMC_NAND_DATA_0);
+
+       /* Ending address at the end of Flash */
+       writeb(NAND_CMD_UNLOCK2, GPMC_NAND_COMMAND_0);
+       writeb(0xc0, GPMC_NAND_ADDRESS_0);
+       writeb(0xff, GPMC_NAND_ADDRESS_0);
+       writeb(0x03, GPMC_NAND_ADDRESS_0);
+       writeb(-1, GPMC_NAND_DATA_0);
+       writeb(0x79, GPMC_NAND_COMMAND_0);
+       writeb(-1, GPMC_NAND_DATA_0);
+       writeb(-1, GPMC_NAND_DATA_0);
+}
 #endif
 
 #ifdef CONFIG_USB_MUSB_OMAP2PLUS
@@ -207,6 +233,16 @@ int board_init(void)
 }
 
 #ifdef CONFIG_BOARD_LATE_INIT
+
+static void unlock_nand(void)
+{
+       int dev = nand_curr_device;
+       struct mtd_info *mtd;
+
+       mtd = get_nand_dev_by_index(dev);
+       nand_unlock(mtd, 0, mtd->size, 0);
+}
+
 int board_late_init(void)
 {
        struct board_id *board;
@@ -256,6 +292,10 @@ int board_late_init(void)
 
        /* restore hsusb0_data5 pin as hsusb0_data5 */
        MUX_VAL(CP(HSUSB0_DATA5),       (IEN  | PTD | DIS | M0));
+
+#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
+       unlock_nand();
+#endif
        return 0;
 }
 #endif