Blackfin: bf537-stamp: use common spi boot workaround code

[u-boot] / board / matrix_vision / mvblm7 / pci.c

diff --git a/board/matrix_vision/mvblm7/pci.c b/board/matrix_vision/mvblm7/pci.c
index ef34a6b453e292a99a6ca4d3332a99985fba2b6d..1cc524bb4004fc8717f0ea933f425e573b3170c8 100644 (file)
--- a/board/matrix_vision/mvblm7/pci.c
+++ b/board/matrix_vision/mvblm7/pci.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
  *
  * (C) Copyright 2008
  * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
@@ -32,51 +32,35 @@
 #include <fpga.h>
 #include "mvblm7.h"
 #include "fpga.h"
+#include "../common/mv_common.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int mvblm7_load_fpga(void)
-{
-       size_t data_size = 0;
-       void *fpga_data = NULL;
-       char *datastr = getenv("fpgadata");
-       char *sizestr = getenv("fpgadatasize");
-
-       if (datastr)
-               fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
-       if (sizestr)
-               data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
-
-       return fpga_load(0, fpga_data, data_size);
-}
-
 static struct pci_region pci_regions[] = {
        {
-               bus_start: CFG_PCI1_MEM_BASE,
-               phys_start: CFG_PCI1_MEM_PHYS,
-               size: CFG_PCI1_MEM_SIZE,
+               bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+               phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+               size: CONFIG_SYS_PCI1_MEM_SIZE,
                flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
        },
        {
-               bus_start: CFG_PCI1_MMIO_BASE,
-               phys_start: CFG_PCI1_MMIO_PHYS,
-               size: CFG_PCI1_MMIO_SIZE,
+               bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+               phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+               size: CONFIG_SYS_PCI1_MMIO_SIZE,
                flags: PCI_REGION_MEM
        },
        {
-               bus_start: CFG_PCI1_IO_BASE,
-               phys_start: CFG_PCI1_IO_PHYS,
-               size: CFG_PCI1_IO_SIZE,
+               bus_start: CONFIG_SYS_PCI1_IO_BASE,
+               phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+               size: CONFIG_SYS_PCI1_IO_SIZE,
                flags: PCI_REGION_IO
        }
 };
 
 void pci_init_board(void)
 {
-       char *s;
        int i;
        int warmboot;
-       int load_fpga;
        volatile immap_t *immr;
        volatile pcictrl83xx_t *pci_ctrl;
        volatile gpio83xx_t *gpio;
@@ -84,32 +68,23 @@ void pci_init_board(void)
        volatile law83xx_t *pci_law;
        struct pci_region *reg[] = { pci_regions };
 
-       load_fpga = 1;
-       immr = (immap_t *) CFG_IMMR;
+       immr = (immap_t *) CONFIG_SYS_IMMR;
        clk = (clk83xx_t *) &immr->clk;
        pci_ctrl = immr->pci_ctrl;
        pci_law = immr->sysconf.pcilaw;
        gpio  = (volatile gpio83xx_t *)&immr->gpio[0];
 
-       s = getenv("skip_fpga");
-       if (s) {
-               printf("found 'skip_fpga' -> FPGA _not_ loaded !\n");
-               load_fpga = 0;
-       }
-
        gpio->dat = MV_GPIO_DAT;
        gpio->odr = MV_GPIO_ODE;
-       if (load_fpga)
-               gpio->dir = MV_GPIO_OUT;
-       else
-               gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK);
+       gpio->dir = MV_GPIO_OUT;
 
        printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh,
                immr->sysconf.sicrl);
 
        mvblm7_init_fpga();
-       if (load_fpga)
-               mvblm7_load_fpga();
+       mv_load_fpga();
+
+       gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK);
 
        /* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */
        clk->occr = 0xc0000000;
@@ -121,10 +96,10 @@ void pci_init_board(void)
        for (i = 0; i < 1000; ++i)
                udelay(1000);
 
-       pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+       pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
        pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB;
 
-       pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+       pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
        pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
 
        warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;