Sequential accesses to non-existent memory must be synchronized,

[u-boot] / board / mcc200 / mcc200.c

diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c
index 71a691b5dbf1fb171b62ad823b603aeef65d8dbb..8b475c690d9d24affb9d3e33930720a130482f23 100644 (file)
--- a/board/mcc200/mcc200.c
+++ b/board/mcc200/mcc200.c
@@ -27,6 +27,7 @@
 #include <common.h>
 #include <mpc5xxx.h>
 #include <pci.h>
+#include <asm/processor.h>
 
 /* Two MT48LC8M32B2 for 32 MB */
 /* #include "mt48lc8m32b2-6-7.h" */
@@ -98,6 +99,7 @@ long int initdram (int board_type)
 {
        ulong dramsize = 0;
        ulong dramsize2 = 0;
+       uint svr, pvr;
 #ifndef CFG_RAMBOOT
        ulong test1, test2;
 
@@ -192,6 +194,23 @@ long int initdram (int board_type)
 
 #endif /* CFG_RAMBOOT */
 
+       /*
+        * On MPC5200B we need to set the special configuration delay in the
+        * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+        * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+        *
+        * "The SDelay should be written to a value of 0x00000004. It is
+        * required to account for changes caused by normal wafer processing
+        * parameters."
+        */
+       svr = get_svr();
+       pvr = get_pvr();
+       if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && 
+           (PVR_MIN(pvr) == 4)) {
+               *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+               __asm__ volatile ("sync");
+       }
+
        return dramsize + dramsize2;
 }