#include <spd.h>
#include <miiphy.h>
#include <command.h>
-#if defined(CONFIG_PCI)
-#include <pci.h>
-#endif
#if defined(CONFIG_SPD_EEPROM)
#include <spd_sdram.h>
#endif
/* Enable flash write */
bcsr[1] &= ~0x01;
+#ifdef CFG_USE_MPC834XSYS_USB_PHY
+ /* Use USB PHY on SYS board */
+ bcsr[5] |= 0x02;
+#endif
+
return 0;
}
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -1;
+ puts("Initializing\n");
+
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
-
- msize = spd_sdram(0);
+ msize = spd_sdram();
#else
msize = fixed_sdram();
#endif
return -1;
}
}
+ im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+
#if (CFG_DDR_SIZE != 256)
#warning Currenly any ddr size other than 256 is not supported
#endif
-
- im->ddr.csbnds[0].csbnds = 0x00100017;
- im->ddr.csbnds[1].csbnds = 0x0018001f;
- im->ddr.csbnds[2].csbnds = 0x00000007;
- im->ddr.csbnds[3].csbnds = 0x0008000f;
- im->ddr.cs_config[0] = CFG_DDR_CONFIG;
- im->ddr.cs_config[1] = CFG_DDR_CONFIG;
+ im->ddr.csbnds[2].csbnds = 0x0000000f;
im->ddr.cs_config[2] = CFG_DDR_CONFIG;
- im->ddr.cs_config[3] = CFG_DDR_CONFIG;
- im->ddr.timing_cfg_1 =
- 3 << TIMING_CFG1_PRETOACT_SHIFT |
- 7 << TIMING_CFG1_ACTTOPRE_SHIFT |
- 3 << TIMING_CFG1_ACTTORW_SHIFT |
- 4 << TIMING_CFG1_CASLAT_SHIFT |
- 3 << TIMING_CFG1_REFREC_SHIFT |
- 3 << TIMING_CFG1_WRREC_SHIFT |
- 2 << TIMING_CFG1_ACTTOACT_SHIFT |
- 1 << TIMING_CFG1_WRTORD_SHIFT;
- im->ddr.timing_cfg_2 = 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT;
+
+ /* currently we use only one CS, so disable the other banks */
+ im->ddr.cs_config[0] = 0;
+ im->ddr.cs_config[1] = 0;
+ im->ddr.cs_config[3] = 0;
+
+ im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
+
im->ddr.sdram_cfg =
SDRAM_CFG_SREN
#if defined(CONFIG_DDR_2T_TIMING)
| SDRAM_CFG_2T_EN
#endif
| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
- im->ddr.sdram_mode =
- 0x2000 << SDRAM_MODE_ESD_SHIFT |
- 0x0162 << SDRAM_MODE_SD_SHIFT;
+#if defined (CONFIG_DDR_32BIT)
+ /* for 32-bit mode burst length is 8 */
+ im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
+#endif
+ im->ddr.sdram_mode = CFG_DDR_MODE;
- im->ddr.sdram_interval = 0x045B << SDRAM_INTERVAL_REFINT_SHIFT |
- 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT;
+ im->ddr.sdram_interval = CFG_DDR_INTERVAL;
udelay(200);
+ /* enable DDR controller */
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-
return msize;
}
#endif/*!CFG_SPD_EEPROM*/
return 0;
}
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI Devices, report devices found
- */
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc8349emds_config_table[] = {
- {PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,
- pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMON_MEMORY | PCI_COMMAND_MASTER
- } },
- {}
-}
-#endif
-
-volatile static struct pci_controller hose[] = {
- {
-#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc8349emds_config_table,
-#endif
- },
- {
-#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc8349emds_config_table,
-#endif
- }
-};
-#endif /* CONFIG_PCI */
-
-void pci_init_board(void)
-{
-#ifdef CONFIG_PCI
- extern void pci_mpc83xx_init(volatile struct pci_controller *hose);
-
- pci_mpc83xx_init(hose);
-#endif /* CONFIG_PCI */
-}
-
/*
* if MPC8349EMDS is soldered with SDRAM
*/
volatile u32 val;
u64 *addr, count, val64;
register u64 *i;
-
+
if (argc > 4) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
-
+
if (argc == 2) {
if (strcmp(argv[1], "status") == 0) {
ecc_print_status();
ddr->capture_attributes = 0;
return 0;
}
- }
-
+ }
+
if (argc == 3) {
if (strcmp(argv[1], "sbecnt") == 0) {
val = simple_strtoul(argv[2], NULL, 10);
} else if (strcmp(argv[2], "+mse") == 0) {
val |= ECC_ERROR_DISABLE_MSED;
} else if (strcmp(argv[2], "+all") == 0) {
- val |= (ECC_ERROR_DISABLE_SBED |
- ECC_ERROR_DISABLE_MBED |
+ val |= (ECC_ERROR_DISABLE_SBED |
+ ECC_ERROR_DISABLE_MBED |
ECC_ERROR_DISABLE_MSED);
} else if (strcmp(argv[2], "-sbe") == 0) {
val &= ~ECC_ERROR_DISABLE_SBED;
} else if (strcmp(argv[2], "-mse") == 0) {
val &= ~ECC_ERROR_DISABLE_MSED;
} else if (strcmp(argv[2], "-all") == 0) {
- val &= ~(ECC_ERROR_DISABLE_SBED |
- ECC_ERROR_DISABLE_MBED |
+ val &= ~(ECC_ERROR_DISABLE_SBED |
+ ECC_ERROR_DISABLE_MBED |
ECC_ERROR_DISABLE_MSED);
} else {
printf("Incorrect err_disable field\n");