mpc83xx: Replace fdt_node_offset() with fdt_find_node_by_path().

[u-boot] / board / mpc8360emds / mpc8360emds.c

diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c
index ddc1047c6188d1109bf0a02d1fad8f20ca9c4b12..f63d3ae65146acf01b518d8249a565cf0401447b 100644 (file)
--- a/board/mpc8360emds/mpc8360emds.c
+++ b/board/mpc8360emds/mpc8360emds.c
@@ -30,6 +30,9 @@
 #endif
 #if defined(CONFIG_OF_FLAT_TREE)
 #include <ft_build.h>
+#elif defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#include <libfdt_env.h>
 #endif
 
 const qe_iop_conf_t qe_iop_conf_tab[] = {
@@ -90,11 +93,20 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
 
 int board_early_init_f(void)
 {
-       volatile u8 *bcsr = (volatile u8 *)CFG_BCSR;
+
+       u8 *bcsr = (u8 *)CFG_BCSR;
+       const immap_t *immr = (immap_t *)CFG_IMMR;
 
        /* Enable flash write */
        bcsr[0xa] &= ~0x04;
 
+       /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2 h/w bug workaround) */
+       if (immr->sysconf.spridr == SPR_8360_REV20 ||
+           immr->sysconf.spridr == SPR_8360E_REV20 ||
+           immr->sysconf.spridr == SPR_8360_REV21 ||
+           immr->sysconf.spridr == SPR_8360E_REV21)
+               bcsr[0xe] = 0x30;
+
        return 0;
 }
 
@@ -158,6 +170,20 @@ int fixed_sdram(void)
 #if (CFG_DDR_SIZE != 256)
 #warning Currenly any ddr size other than 256 is not supported
 #endif
+#ifdef CONFIG_DDR_II
+       im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
+       im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
+       im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
+       im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
+       im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
+       im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
+       im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
+       im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
+       im->ddr.sdram_mode = CFG_DDR_MODE;
+       im->ddr.sdram_mode2 = CFG_DDR_MODE2;
+       im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+       im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
+#else
        im->ddr.csbnds[0].csbnds = 0x00000007;
        im->ddr.csbnds[1].csbnds = 0x0008000f;
 
@@ -170,6 +196,7 @@ int fixed_sdram(void)
 
        im->ddr.sdram_mode = CFG_DDR_MODE;
        im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+#endif
        udelay(200);
        im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 
@@ -636,22 +663,45 @@ U_BOOT_CMD(ecc, 4, 0, do_ecc,
           "  - disables injects\n" "  - re-inits memory");
 #endif                         /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */
 
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+#if (defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)) \
+     && defined(CONFIG_OF_BOARD_SETUP)
+
+/*
+ * Prototypes of functions that we use.
+ */
+void ft_cpu_setup(void *blob, bd_t *bd);
+
+#ifdef CONFIG_PCI
+void ft_pci_setup(void *blob, bd_t *bd);
+#endif
+
 void
 ft_board_setup(void *blob, bd_t *bd)
 {
+#if defined(CONFIG_OF_LIBFDT)
+       int nodeoffset;
+       int tmp[2];
+
+       nodeoffset = fdt_find_node_by_path(fdt, "/memory");
+       if (nodeoffset >= 0) {
+               tmp[0] = cpu_to_be32(bd->bi_memstart);
+               tmp[1] = cpu_to_be32(bd->bi_memsize);
+               fdt_setprop(fdt, nodeoffset, "reg", tmp, sizeof(tmp));
+       }
+#else
        u32 *p;
        int len;
 
-#ifdef CONFIG_PCI
-       ft_pci_setup(blob, bd);
-#endif
-       ft_cpu_setup(blob, bd);
-
        p = ft_get_prop(blob, "/memory/reg", &len);
        if (p != NULL) {
                *p++ = cpu_to_be32(bd->bi_memstart);
                *p = cpu_to_be32(bd->bi_memsize);
        }
-}
 #endif
+
+#ifdef CONFIG_PCI
+       ft_pci_setup(blob, bd);
+#endif
+       ft_cpu_setup(blob, bd);
+}
+#endif /* CONFIG_OF_x */