Merge branch 'master' of git://git.denx.de/u-boot-i2c

[u-boot] / board / mpc8540eval / mpc8540eval.c

diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c
index fa0a33686664e91b47ef126234b42eef62a078d5..054d644d951bd9781f46fd40fe4d2251e7ee07f6 100644 (file)
--- a/board/mpc8540eval/mpc8540eval.c
+++ b/board/mpc8540eval/mpc8540eval.c
@@ -50,7 +50,7 @@ int checkboard (void)
        get_sys_info (&sysinfo);
 
        printf ("Board: Freescale MPC8540EVAL Board\n");
-       printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+       printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor[0] / 1000000);
        printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
        printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
        if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \
@@ -69,7 +69,7 @@ phys_size_t initdram (int board_type)
        long dram_size = 0;
 
 #if !defined(CONFIG_RAM_AS_FLASH)
-       volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+       volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
        sys_info_t sysinfo;
        uint temp_lbcdll = 0;
 #endif
@@ -101,7 +101,7 @@ phys_size_t initdram (int board_type)
 #if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
        get_sys_info(&sysinfo);
        /* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */
-       if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) {
+       if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV) < 66000000) {
                lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000;
        } else {
                lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff;
@@ -110,8 +110,8 @@ phys_size_t initdram (int board_type)
                gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
                asm("sync;isync;msync");
        }
-       lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */
-       lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+       set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); /* 64MB SDRAM */
+       set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
        lbc->lbcr = CONFIG_SYS_LBC_LBCR;
        lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
        asm("sync");
@@ -137,40 +137,9 @@ phys_size_t initdram (int board_type)
        {
                /* Initialize all of memory for ECC, then
                 * enable errors */
-               uint *p = 0;
-               uint i = 0;
                volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
-               dma_init();
-               for (*p = 0; p < (uint *)(8 * 1024); p++) {
-                       if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
-                       *p = (unsigned int)0xdeadbeef;
-                       if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
-               }
-
-               /* 8K */
-               dma_xfer((uint *)0x2000,0x2000,(uint *)0);
-               /* 16K */
-               dma_xfer((uint *)0x4000,0x4000,(uint *)0);
-               /* 32K */
-               dma_xfer((uint *)0x8000,0x8000,(uint *)0);
-               /* 64K */
-               dma_xfer((uint *)0x10000,0x10000,(uint *)0);
-               /* 128k */
-               dma_xfer((uint *)0x20000,0x20000,(uint *)0);
-               /* 256k */
-               dma_xfer((uint *)0x40000,0x40000,(uint *)0);
-               /* 512k */
-               dma_xfer((uint *)0x80000,0x80000,(uint *)0);
-               /* 1M */
-               dma_xfer((uint *)0x100000,0x100000,(uint *)0);
-               /* 2M */
-               dma_xfer((uint *)0x200000,0x200000,(uint *)0);
-               /* 4M */
-               dma_xfer((uint *)0x400000,0x400000,(uint *)0);
 
-               for (i = 1; i < dram_size / 0x800000; i++) {
-                       dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
-               }
+               dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
 
                /* Enable errors for ECC */
                ddr->err_disable = 0x00000000;