Merge with testing-NAND (Rewrite of NAND code)

[u-boot] / board / mpl / common / pci_parts.h

diff --git a/board/mpl/common/pci_parts.h b/board/mpl/common/pci_parts.h
index 944585f356ae208fa0cc2ee83c3365b125d29631..a57b12156192e7f1e5ffebe94de24722bc9307c8 100644 (file)
--- a/board/mpl/common/pci_parts.h
+++ b/board/mpl/common/pci_parts.h
@@ -59,7 +59,6 @@
 #define PCI_IRQ_VECTOR(x)      ((PCI_DEV(x) + 10) % 4) + 28
 
 
-
 /* PCI Device List for PIP405 */
 
 /* Mapping:
@@ -93,7 +92,7 @@ extern void pci_pip405_write_regs(struct pci_controller *,
 /* PIIX4 ISA Bridge Function 0 */
 static struct pci_pip405_config_entry piix4_isa_bridge_f0[] = {
        {PCI_CFG_PIIX4_SERIRQ,  0xD0,           1}, /* enable Continous SERIRQ Pin */
-       {PCI_CFG_PIIX4_GENCFG,  0x00010041,     4}, /* enable SERIRQs, ISA, PNP */
+       {PCI_CFG_PIIX4_GENCFG,  0x00018041,     4}, /* enable SERIRQs, ISA, PNP, GPI11 */
        {PCI_CFG_PIIX4_TOM,     0xFE,           1}, /* Top of Memory            */
        {PCI_CFG_PIIX4_XBCS,    0x02C4,         2}, /* disable all peri CS      */
        {PCI_CFG_PIIX4_RTCCFG,  0x21,           1}, /* enable RTC               */
@@ -107,27 +106,34 @@ static struct pci_pip405_config_entry piix4_isa_bridge_f0[] = {
 
 /* PIIX4 IDE Controller Function 1 */
 static struct pci_pip405_config_entry piix4_ide_cntrl_f1[] = {
+       {PCI_CFG_PIIX4_BMIBA,   0x0001000,      4}, /* set BMI to a valid address */
        {PCI_COMMAND,           0x0001,         2}, /* enable IO access         */
+#if !defined(CONFIG_MIP405T)
        {PCI_CFG_PIIX4_IDETIM,  0x80008000,     4}, /* enable Both IDE channels */
+#else
+       {PCI_CFG_PIIX4_IDETIM,  0x00008000,     4}, /* enable IDE channel0      */
+#endif
        { }                                         /* end of device table      */
 };
 
 /* PIIX4 USB Controller Function 2 */
 static struct pci_pip405_config_entry piix4_usb_cntrl_f2[] = {
+#if !defined(CONFIG_MIP405T)
        {PCI_INTERRUPT_LINE,    31,             1}, /* Int vector = 31          */
        {PCI_BASE_ADDRESS_4,    0x0000E001,     4}, /* Set IO Address to 0xe000 to 0xe01F */
        {PCI_LATENCY_TIMER,     0x80,           1}, /* Latency Timer 0x80       */
        {0xC0,                  0x2000,         2}, /* Legacy support           */
        {PCI_COMMAND,           0x0005,         2}, /* enable IO access and Master */
+#endif
        { }                                         /* end of device table      */
 };
 
 /* PIIX4 Power Management Function 3 */
 static struct pci_pip405_config_entry piix4_pmm_cntrl_f3[] = {
-       {PCI_COMMAND,           0x0001,         2}, /* enable IO access         */
-       {PCI_CFG_PIIX4_PMAB,    0x00004000,     4}, /* set PMBA to "valid" value */
-       {PCI_CFG_PIIX4_PMMISC,  0x01,           1}, /* enable PMBA IO access    */
+       {PCI_CFG_PIIX4_PMBA,    0x00004000,     4}, /* set PMBA to "valid" value */
        {PCI_CFG_PIIX4_SMBBA,   0x00005000,     4}, /* set SMBBA to "valid" value */
+       {PCI_CFG_PIIX4_PMMISC,  0x01,           1}, /* enable PMBA IO access    */
+       {PCI_COMMAND,           0x0001,         2}, /* enable IO access         */
        { }                                         /* end of device table      */
 };
 /* PPC405 Dummy only used to prevent autosetup on this host bridge */
@@ -185,8 +191,3 @@ static struct pci_config_table pci_pip405_config_table[]={
        { }
 };
 #endif /* _PCI_PARTS_H_ */
-
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