Cleanup for GCC-4.x

[u-boot] / board / mpl / pip405 / pip405.c

diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c
index a77e2c9ba4f7863cb80f70f049f6e870a70e1577..a398362f96aef4fad6eab5f3f77e22681ba831f0 100644 (file)
--- a/board/mpl/pip405/pip405.c
+++ b/board/mpl/pip405/pip405.c
@@ -176,11 +176,11 @@ void write_4hex (unsigned long val)
 
 #endif
 
-int board_pre_init (void)
+int board_early_init_f (void)
 {
        unsigned char dataout[1];
        unsigned char datain[128];
-       unsigned long sdram_size;
+       unsigned long sdram_size = 0;
        SDRAM_SETUP *t = (SDRAM_SETUP *) sdram_setup_table;
        unsigned long memclk;
        unsigned long tmemclk = 0;
@@ -194,6 +194,11 @@ int board_pre_init (void)
 #ifdef SDRAM_DEBUG
        DECLARE_GLOBAL_DATA_PTR;
 #endif
+       /* set up the config port */
+       mtdcr (ebccfga, pb7ap);
+       mtdcr (ebccfgd, CONFIG_PORT_AP);
+       mtdcr (ebccfga, pb7cr);
+       mtdcr (ebccfgd, CONFIG_PORT_CR);
 
        memclk = get_bus_freq (tmemclk);
        tmemclk = 1000000000 / (memclk / 100);  /* in 10 ps units */
@@ -569,15 +574,15 @@ int board_pre_init (void)
 
 int checkboard (void)
 {
-       unsigned char s[50];
+       char s[50];
        unsigned char bc;
        int i;
        backup_t *b = (backup_t *) s;
 
        puts ("Board: ");
 
-       i = getenv_r ("serial#", s, 32);
-       if ((i == 0) || strncmp (s, "PIP405", 6)) {
+       i = getenv_r ("serial#", (char *)s, 32);
+       if ((i == 0) || strncmp ((char *)s, "PIP405", 6)) {
                get_backup_values (b);
                if (strncmp (b->signature, "MPL\0", 4) != 0) {
                        puts ("### No HW ID - assuming PIP405");
@@ -657,8 +662,20 @@ static int test_dram (unsigned long ramsize)
 }
 
 
+extern flash_info_t flash_info[];      /* info for FLASH chips */
+
 int misc_init_r (void)
 {
+       DECLARE_GLOBAL_DATA_PTR;
+       /* adjust flash start and size as well as the offset */
+       gd->bd->bi_flashstart=0-flash_info[0].size;
+       gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN;
+       gd->bd->bi_flashoffset=0;
+
+       /* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
+       if (mfdcr(strap) & PSR_ROM_LOC)
+              mtspr(ccr0, (mfspr(ccr0) & ~0x80));
+
        return (0);
 }