* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
- * (C) Copyright 2002
+ * (C) Copyright 2002, 2010
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
*
* See file CREDITS for list of people who contributed to this
*/
#include <common.h>
-#include <s3c2410.h>
+#include <netdev.h>
#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/s3c24x0_cpu.h>
#include "vcma9.h"
#include "../common/common_util.h"
-/* ------------------------------------------------------------------------- */
-
-#define FCLK_SPEED 1
-
-#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
-#define M_MDIV 0xC3
-#define M_PDIV 0x4
-#define M_SDIV 0x1
-#elif FCLK_SPEED==1 /* Fout = 202.8MHz */
-#define M_MDIV 0xA1
-#define M_PDIV 0x3
-#define M_SDIV 0x1
-#endif
-
-#define USB_CLOCK 1
-
-#if USB_CLOCK==0
-#define U_M_MDIV 0xA1
-#define U_M_PDIV 0x3
-#define U_M_SDIV 0x1
-#elif USB_CLOCK==1
-#define U_M_MDIV 0x48
-#define U_M_PDIV 0x3
-#define U_M_SDIV 0x2
-#endif
-
-static inline void delay(unsigned long loops)
-{
- __asm__ volatile ("1:\n"
- "subs %0, %1, #1\n"
- "bne 1b":"=r" (loops):"0" (loops));
-}
+DECLARE_GLOBAL_DATA_PTR;
/*
* Miscellaneous platform dependent initialisations
*/
-int board_init(void)
+int board_early_init_f(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
- /* to reduce PLL lock time, adjust the LOCKTIME register */
- rLOCKTIME = 0xFFFFFF;
-
- /* configure MPLL */
- rMPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
-
- /* some delay between MPLL and UPLL */
- delay (4000);
-
- /* configure UPLL */
- rUPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
-
- /* some delay between MPLL and UPLL */
- delay (8000);
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* set up the I/O ports */
- rGPACON = 0x007FFFFF;
- rGPBCON = 0x002AAAAA;
- rGPBUP = 0x000002BF;
- rGPCCON = 0xAAAAAAAA;
- rGPCUP = 0x0000FFFF;
- rGPDCON = 0xAAAAAAAA;
- rGPDUP = 0x0000FFFF;
- rGPECON = 0xAAAAAAAA;
- rGPEUP = 0x000037F7;
- rGPFCON = 0x00000000;
- rGPFUP = 0x00000000;
- rGPGCON = 0xFFEAFF5A;
- rGPGUP = 0x0000F0DC;
- rGPHCON = 0x0028AAAA;
- rGPHUP = 0x00000656;
-
- /* setup correct IRQ modes for NIC */
- rEXTINT2 = (rEXTINT2 & ~(7<<8)) | (4<<8); /* rising edge mode */
-
- /* init serial */
- gd->baudrate = CONFIG_BAUDRATE;
- gd->have_console = 1;
- serial_init();
-
- /* arch number of VCMA9-Board */
- gd->bd->bi_arch_number = 227;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0x30000100;
-
- icache_enable();
- dcache_enable();
+ writel(0x007FFFFF, &gpio->gpacon);
+ writel(0x002AAAAA, &gpio->gpbcon);
+ writel(0x000002BF, &gpio->gpbup);
+ writel(0xAAAAAAAA, &gpio->gpccon);
+ writel(0x0000FFFF, &gpio->gpcup);
+ writel(0xAAAAAAAA, &gpio->gpdcon);
+ writel(0x0000FFFF, &gpio->gpdup);
+ writel(0xAAAAAAAA, &gpio->gpecon);
+ writel(0x000037F7, &gpio->gpeup);
+ writel(0x00000000, &gpio->gpfcon);
+ writel(0x00000000, &gpio->gpfup);
+ writel(0xFFEAFF5A, &gpio->gpgcon);
+ writel(0x0000F0DC, &gpio->gpgup);
+ writel(0x0028AAAA, &gpio->gphcon);
+ writel(0x00000656, &gpio->gphup);
+
+ /* setup correct IRQ modes for NIC (rising edge mode) */
+ writel((readl(&gpio->extint2) & ~(7<<8)) | (4<<8), &gpio->extint2);
+
+ /* select USB port 2 to be host or device (setup as host for now) */
+ writel(readl(&gpio->misccr) | 0x08, &gpio->misccr);
return 0;
}
-int dram_init(void)
+int board_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0x30000100;
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ icache_enable();
+ dcache_enable();
return 0;
}
* Get some Board/PLD Info
*/
-static uchar Get_PLD_ID(void)
+static u8 get_pld_reg(enum vcma9_pld_regs reg)
+{
+ return readb(VCMA9_PLD_BASE + reg);
+}
+
+static u8 get_pld_version(void)
{
- return(*(volatile uchar *)PLD_ID_REG);
+ return (get_pld_reg(VCMA9_PLD_ID) >> 4) & 0x0F;
}
-static uchar Get_PLD_BOARD(void)
+static u8 get_pld_revision(void)
{
- return(*(volatile uchar *)PLD_BOARD_REG);
+ return get_pld_reg(VCMA9_PLD_ID) & 0x0F;
}
-static uchar Get_PLD_Version(void)
+static uchar get_board_pcb(void)
{
- return((Get_PLD_ID() >> 4) & 0x0F);
+ return ((get_pld_reg(VCMA9_PLD_BOARD) >> 4) & 0x03) + 'A';
}
-static uchar Get_PLD_Revision(void)
+static u8 get_nr_chips(void)
{
- return(Get_PLD_ID() & 0x0F);
+ switch ((get_pld_reg(VCMA9_PLD_SDRAM) >> 4) & 0x0F) {
+ case 0: return 4;
+ case 1: return 1;
+ case 2: return 2;
+ default: return 0;
+ }
}
-static int Get_Board_Config(void)
+static ulong get_chip_size(void)
{
- uchar config = Get_PLD_BOARD() & 0x03;
+ switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) {
+ case 0: return 16 * (1024*1024);
+ case 1: return 32 * (1024*1024);
+ case 2: return 8 * (1024*1024);
+ case 3: return 8 * (1024*1024);
+ default: return 0;
+ }
+}
- if (config == 3)
- return 1;
- else
- return 0;
+static const char *get_chip_geom(void)
+{
+ switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) {
+ case 0: return "4Mx8x4";
+ case 1: return "8Mx8x4";
+ case 2: return "2Mx8x4";
+ case 3: return "4Mx8x2";
+ default: return "unknown";
+ }
}
-static uchar Get_Board_PCB(void)
+static void vcma9_show_info(char *board_name, char *serial)
{
- return(((Get_PLD_BOARD() >> 4) & 0x03) + 'A');
+ printf("Board: %s SN: %s PCB Rev: %c PLD(%d,%d)\n",
+ board_name, serial,
+ get_board_pcb(), get_pld_version(), get_pld_revision());
+ printf("SDRAM: %d chips %s\n", get_nr_chips(), get_chip_geom());
}
-/* ------------------------------------------------------------------------- */
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_chip_size() * get_nr_chips();
+ return 0;
+}
/*
* Check Board Identity:
int checkboard(void)
{
- unsigned char s[50];
- unsigned char bc, var, rc;
+ char s[50];
int i;
backup_t *b = (backup_t *) s;
- puts("Board: ");
-
- i = getenv_r("serial#", s, 32);
+ i = getenv_f("serial#", s, 32);
if ((i < 0) || strncmp (s, "VCMA9", 5)) {
get_backup_values (b);
if (strncmp (b->signature, "MPL\0", 4) != 0) {
puts ("### No HW ID - assuming VCMA9");
} else {
b->serial_name[5] = 0;
- printf ("%s-%d Rev %c SN: %s", b->serial_name, Get_Board_Config(),
- Get_Board_PCB(), &b->serial_name[6]);
+ vcma9_show_info(b->serial_name, &b->serial_name[6]);
}
} else {
s[5] = 0;
- printf ("%s-%d Rev %c SN: %s", s, Get_Board_Config(), Get_Board_PCB(),
- &s[6]);
+ vcma9_show_info(s, &s[6]);
}
- printf("\n");
- return(0);
-}
-
-
-void print_vcma9_rev(void)
-{
- printf("Board: VCMA9-%d Rev: %c (PLD Ver: %d, Rev: %d)\n",
- Get_Board_Config(), Get_Board_PCB(),
- Get_PLD_Version(), Get_PLD_Revision());
+ return 0;
}
-
-int last_stage_init(void)
+int board_late_init(void)
{
- print_vcma9_rev();
- show_stdio_dev();
+ /*
+ * check if environment is healthy, otherwise restore values
+ * from shadow copy
+ */
check_env();
return 0;
}
-/***************************************************************************
- * some helping routines
- */
-
-int overwrite_console(void)
+void vcma9_print_info(void)
{
- /* return TRUE if console should be overwritten */
- return 0;
-}
+ char *s = getenv("serial#");
+ if (!s) {
+ puts ("### No HW ID - assuming VCMA9");
+ } else {
+ s[5] = 0;
+ vcma9_show_info(s, &s[6]);
+ }
+}
-/************************************************************************
-* Print VCMA9 Info
-************************************************************************/
-void print_vcma9_info(void)
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
{
- print_vcma9_rev();
+ int rc = 0;
+#ifdef CONFIG_CS8900
+ rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
+#endif
+ return rc;
}
+#endif
-
+/*
+ * Hardcoded flash setup:
+ * Flash 0 is a non-CFI AMD AM29F400BB flash.
+ */
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ info->portwidth = FLASH_CFI_16BIT;
+ info->chipwidth = FLASH_CFI_BY16;
+ info->interface = FLASH_CFI_X16;
+ return 1;
+}
projects / u-boot / blobdiff