Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org>
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
-#include <version.h>
#include <asm/processor.h>
+#include <asm/macro.h>
#ifdef CONFIG_CPU_SH7751
#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
lowlevel_init:
- mov.l CCR_A, r1 ! CCR Address
- mov.l CCR_D_DISABLE, r0 ! CCR Data
- mov.l r0, @r1
+ write32 CCR_A, CCR_D_DISABLE
init_bsc:
- mov.l FRQCR_A, r1 /* FRQCR Address */
- mov.l FRQCR_D, r0 /* FRQCR Data */
- mov.w r0, @r1
+ write16 FRQCR_A, FRQCR_D
- mov.l BCR1_A, r1 /* BCR1 Address */
- mov.l BCR1_D, r0 /* BCR1 Data */
- mov.l r0, @r1
+ write32 BCR1_A, BCR1_D
- mov.l BCR2_A, r1 /* BCR2 Address */
- mov.l BCR2_D, r0 /* BCR2 Data */
- mov.w r0, @r1
+ write16 BCR2_A, BCR2_D
- mov.l WCR1_A, r1 /* WCR1 Address */
- mov.l WCR1_D, r0 /* WCR1 Data */
- mov.l r0, @r1
+ write32 WCR1_A, WCR1_D
- mov.l WCR2_A, r1 /* WCR2 Address */
- mov.l WCR2_D, r0 /* WCR2 Data */
- mov.l r0, @r1
+ write32 WCR2_A, WCR2_D
- mov.l WCR3_A, r1 /* WCR3 Address */
- mov.l WCR3_D, r0 /* WCR3 Data */
- mov.l r0, @r1
+ write32 WCR3_A, WCR3_D
- mov.l MCR_A, r1 /* MCR Address */
- mov.l MCR_D1, r0 /* MCR Data1 */
- mov.l r0, @r1
+ write32 MCR_A, MCR_D1
- mov.l SDMR3_A, r1 /* Set SDRAM mode */
- mov #0, r0
- mov.b r0, @r1
+ /* Set SDRAM mode */
+ write8 SDMR3_A, SDMR3_D
! Do you need PCMCIA setting?
! If so, please add the lines here...
- mov.l RTCNT_A, r1 /* RTCNT Address */
- mov.l RTCNT_D, r0 /* RTCNT Data */
- mov.w r0, @r1
+ write16 RTCNT_A, RTCNT_D
- mov.l RTCOR_A, r1 /* RTCOR Address */
- mov.l RTCOR_D, r0 /* RTCOR Data */
- mov.w r0, @r1
+ write16 RTCOR_A, RTCOR_D
- mov.l RTCSR_A, r1 /* RTCSR Address */
- mov.l RTCSR_D, r0 /* RTCSR Data */
- mov.w r0, @r1
+ write16 RTCSR_A, RTCSR_D
+
+ write16 RFCR_A, RFCR_D
- mov.l RFCR_A, r1 /* RFCR Address */
- mov.l RFCR_D, r0 /* RFCR Data */
- mov.w r0, @r1 /* Clear reflesh counter */
/* Wait DRAM refresh 30 times */
mov #30, r3
1:
cmp/hi r3, r2
bf 1b
- mov.l MCR_A, r1 /* MCR Address */
- mov.l MCR_D2, r0 /* MCR Data2 */
- mov.l r0, @r1
+ write32 MCR_A, MCR_D2
- mov.l SDMR3_A, r1 /* Set SDRAM mode */
- mov #0, r0
- mov.b r0, @r1
+ /* Set SDRAM mode */
+ write8 SDMR3_A, SDMR3_D
rts
nop
FRQCR_A: .long FRQCR
FRQCR_D:
#ifdef CONFIG_CPU_TYPE_R
- .long 0x00000e1a /* 12:3:3 */
+ .word 0x0e1a /* 12:3:3 */
#else /* CONFIG_CPU_TYPE_R */
#ifdef CONFIG_GOOD_SESH4
- .long 0x00000e13 /* 6:2:1 */
+ .word 0x00e13 /* 6:2:1 */
#else
- .long 0x00000e23 /* 6:1:1 */
+ .word 0x00e23 /* 6:1:1 */
#endif
+.align 2
#endif /* CONFIG_CPU_TYPE_R */
BCR1_A: .long BCR1
WCR3_A: .long WCR3
WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */
RTCSR_A: .long RTCSR
-RTCSR_D: .long 0xA518 /* RTCSR Write Code A5h Data 18h */
+RTCSR_D: .word 0xA518 /* RTCSR Write Code A5h Data 18h */
+.align 2
RTCNT_A: .long RTCNT
-RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */
+RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */
+.align 2
RTCOR_A: .long RTCOR
-RTCOR_D: .long RTCOR_D_VALUE /* Set refresh time (about 15us) */
+RTCOR_D: .word RTCOR_D_VALUE /* Set refresh time (about 15us) */
+.align 2
SDMR3_A: .long SDMR3_ADDRESS
+SDMR3_D: .long 0x00
MCR_A: .long MCR
MCR_D1: .long MCR_D1_VALUE
MCR_D2: .long MCR_D2_VALUE
RFCR_A: .long RFCR
-RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */
+RFCR_D: .word 0xA400 /* RFCR Write Code A4h Data 00h */
+.align 2