*/
#include <common.h>
+#include <netdev.h>
/*#include <mc9328.h>*/
#include <asm/arch/imx-regs.h>
GPCR = 0x000003AB; /* I/O pad driving strength */
- /* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */
-/* MX1_CS1L = 0x11110601; */
+ /* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */
+/* MX1_CS1L = 0x11110601; */
MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */
return 0;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_CS8900
+ rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
+#endif
+ return rc;
+}
+#endif