+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2012
* Ивайло Димитров <freemangordon@abv.bg>
*
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
params->u.core.rootdev = 0x0;
/* append omap atag only if env setup_omap_atag is set to 1 */
- str = getenv("setup_omap_atag");
+ str = env_get("setup_omap_atag");
if (!str || str[0] != '1')
return;
- str = getenv("setup_console_atag");
+ str = env_get("setup_console_atag");
if (str && str[0] == '1')
setup_console_atag = 1;
else
setup_console_atag = 0;
- setup_boot_reason_atag = getenv("setup_boot_reason_atag");
- setup_boot_mode_atag = getenv("setup_boot_mode_atag");
+ setup_boot_reason_atag = env_get("setup_boot_reason_atag");
+ setup_boot_mode_atag = env_get("setup_boot_mode_atag");
params = *in_params;
t = (struct tag_omap *)¶ms->u;
do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
}
+void omap3_set_aux_cr_secure(u32 acr)
+{
+ struct emu_hal_params_rx51 emu_romcode_params = { 0, };
+
+ emu_romcode_params.num_params = 2;
+ emu_romcode_params.param1 = acr;
+
+ omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
+ (u32 *)&emu_romcode_params);
+}
+
/*
* Routine: omap3_update_aux_cr_secure_rx51
* Description: Modify the contents Auxiliary Control Register.
*/
static void omap3_update_aux_cr_secure_rx51(u32 set_bits, u32 clear_bits)
{
- struct emu_hal_params_rx51 emu_romcode_params = { 0, };
u32 acr;
/* Read ACR */
asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
acr &= ~clear_bits;
acr |= set_bits;
-
- emu_romcode_params.num_params = 2;
- emu_romcode_params.param1 = acr;
-
- omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
- (u32 *)&emu_romcode_params);
+ omap3_set_aux_cr_secure(acr);
}
/*
/* set env variable attkernaddr for relocated kernel */
sprintf(buf, "%#x", KERNEL_ADDRESS);
- setenv("attkernaddr", buf);
+ env_set("attkernaddr", buf);
/* initialize omap tags */
init_omap_tags();
/* reuse atags from previous bootloader */
reuse_atags();
- dieid_num_r();
+ omap_die_id_display();
print_cpuinfo();
/*
* Cortex-A8(r1p0..r1p2) errata 430973 workaround
* Set IBE bit in Auxiliary Control Register
+ *
+ * Call this routine only on real secure device
+ * Qemu does not implement secure PPA and crash
*/
- omap3_update_aux_cr_secure_rx51(1 << 6, 0);
+ if (get_device_type() == HS_DEVICE)
+ omap3_update_aux_cr_secure_rx51(1 << 6, 0);
return 0;
}