#include <asm/arch/mem.h>
#include <i2c.h>
#include <asm/mach-types.h>
+#if defined(CONFIG_CMD_NAND)
+#include <linux/mtd/nand_legacy.h>
+extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
-static void wait_for_command_complete(unsigned int wd_base);
+void wait_for_command_complete(unsigned int wd_base);
/*******************************************************
* Routine: delay
******************************************************/
static inline void delay (unsigned long loops)
{
- __asm__ volatile ("1:\n"
- "subs %0, %1, #1\n"
- "bne 1b":"=r" (loops):"0" (loops));
+ __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0" (loops));
}
/*****************************************
*****************************************/
int board_init (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_PARTIAL_SRAM
- s_init(0x0); /* full sram build, never skip clock and sdrc, no point */
-#else
- gpmc_init();
-#endif
+ gpmc_init(); /* in SRAM or SDRM, finish GPMC */
+
gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4; /* board id for linux */
gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0+0x100); /* adress of boot parameters */
return 0;
}
+/**********************************************************
+ * Routine: try_unlock_sram()
+ * Description: If chip is GP type, unlock the SRAM for
+ * general use.
+ ***********************************************************/
+void try_unlock_sram(void)
+{
+ /* if GP device unlock device SRAM for general use */
+ if (get_device_type() == GP_DEVICE) {
+ __raw_writel(0xFF, A_REQINFOPERM0);
+ __raw_writel(0xCFDE, A_READPERM0);
+ __raw_writel(0xCFDE, A_WRITEPERM0);
+ }
+}
+
/**********************************************************
* Routine: s_init
* Description: Does early system init of muxing and clocks.
- * - Called at time when only stack is available.
+ * - Called path is with sram stack.
**********************************************************/
-void s_init(int skip)
+void s_init(void)
{
+ int in_sdram = running_in_sdram();
+
watchdog_init();
set_muxconf_regs();
delay(100);
+ try_unlock_sram();
- if (!skip)
+ if(!in_sdram)
prcm_init();
peripheral_enable();
icache_enable();
-#ifndef CONFIG_APTIX
- if (!skip)
- memif_init();
-#endif
+ if (!in_sdram)
+ sdrc_init();
}
/*******************************************************
*****************************************/
void watchdog_init(void)
{
- int mode;
-#define GP (BIT8|BIT9)
-
/* There are 4 watch dogs. 1 secure, and 3 general purpose.
- * I would expect that the ROM takes care of the secure one,
- * but we will try also. Of the 3 GP ones, 1 can reset us
- * directly, the other 2 only generate MPU interrupts.
- */
- mode = (__raw_readl(CONTROL_STATUS) & (BIT8|BIT9));
- if (mode == GP) {
- __raw_writel(WD_UNLOCK1 ,WD1_BASE+WSPR);
- wait_for_command_complete(WD1_BASE);
- __raw_writel(WD_UNLOCK2 ,WD1_BASE+WSPR);
- }
+ * The ROM takes care of the secure one. Of the 3 GP ones,
+ * 1 can reset us directly, the other 2 only generate MPU interrupts.
+ */
__raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR);
wait_for_command_complete(WD2_BASE);
__raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR);
* Routine: wait_for_command_complete
* Description: Wait for posting to finish on watchdog
******************************************************/
-static void wait_for_command_complete(unsigned int wd_base)
+void wait_for_command_complete(unsigned int wd_base)
{
int pending = 1;
do {
/*******************************************************************
* Routine:ether_init
* Description: take the Ethernet controller out of reset and wait
- * for the EEPROM load to complete.
+ * for the EEPROM load to complete.
******************************************************************/
void ether_init (void)
{
#ifdef CONFIG_DRIVER_LAN91C96
int cnt = 20;
+ __raw_writeb(0x3,OMAP2420_CTRL_BASE+0x10a); /*protect->gpio95 */
+
__raw_writew(0x0, LAN_RESET_REGISTER);
do {
__raw_writew(0x1, LAN_RESET_REGISTER);
**********************************************/
int dram_init (void)
{
- DECLARE_GLOBAL_DATA_PTR;
unsigned int size0=0,size1=0;
- u32 mtype, btype;
-#define NOT_EARLY 0
+ u32 mtype, btype, rev, cpu;
+ u8 chg_on = 0x5; /* enable charge of back up battery */
+ u8 vmode_on = 0x8C;
+ #define NOT_EARLY 0
- i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); /* need this a bit early */
+ i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /* need this a bit early */
btype = get_board_type();
mtype = get_mem_type();
+ rev = get_cpu_rev();
+ cpu = get_cpu_type();
display_board_info(btype);
- if (btype == BOARD_H4_MENELAUS)
- update_mux(btype,mtype);
+ if (btype == BOARD_H4_MENELAUS){
+ update_mux(btype,mtype); /* combo part on menelaus */
+ i2c_write(I2C_MENELAUS, 0x20, 1, &chg_on, 1); /*fix POR reset bug */
+ i2c_write(I2C_MENELAUS, 0x2, 1, &vmode_on, 1); /* VCORE change on VMODE */
+ }
if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); /* init other chip select */
- size0 = size1 = SZ_32M;
- } else
- size0 = SZ_64M;
+ }
+ size0 = get_sdr_cs_size(SDRC_CS0_OSET);
+ size1 = get_sdr_cs_size(SDRC_CS1_OSET);
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = size0;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ if(rev == CPU_2420_2422_ES1) /* ES1's 128MB remap granularity isn't worth doing */
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ else /* ES2 and above can remap at 32MB granularity */
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0;
gd->bd->bi_dram[1].size = size1;
return 0;
__raw_writel(v, CM_CLKSEL2_CORE);
__raw_writel(0x1, CM_CLKSEL_WKUP);
-#ifdef CFG_NS16550
+#ifdef CONFIG_SYS_NS16550
/* Enable UART1 clock */
func_clks |= BIT21;
if_clks |= BIT21;
/* CAMERA_RSTZ pin configuration, PIN = Y16 */
/* CAM_RST is connected through the I2C IO expander.*/
/* MuxConfigReg = (volatile unsigned char *), CONTROL_PADCONF_SYS_NRESWARM*/
- /* *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+ /* *MuxConfigReg = 0x00 ; / * Mode = 0, PUPD=Disabled */
/* CAMERA_XCLK pin configuration, PIN = U3 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_XCLK;
void muxSetupGPMC(void)
{
volatile uint8 *MuxConfigReg;
- volatile unsigned int *MCR = 0x4800008C;
+ volatile unsigned int *MCR = (volatile unsigned int *)0x4800008C;
/* gpmc_io_dir */
*MCR = 0x19000000;
/* signal - Gpmc_ncs2; pin - E2; offset - 0x008C; mode - 0; Byte-2 Pull/up - N/A */
MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE2,
*MuxConfigReg = 0x00 ;
-
-
}
/****************************************************************
}
}
}
+
+#if defined(CONFIG_CMD_NAND)
+void nand_init(void)
+{
+ extern flash_info_t flash_info[];
+
+ nand_probe(CONFIG_SYS_NAND_ADDR);
+ if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
+ print_size(nand_dev_desc[0].totlen, "\n");
+ }
+
+#ifdef CONFIG_SYS_JFFS2_MEM_NAND
+ flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id;
+ flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].size = 1024*1024*2; /* only read kernel single meg partition */
+ flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].sector_count = 1024; /* 1024 blocks in 16meg chip (use less for raw/copied partition) */
+ flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].start[0] = 0x80200000; /* ?, ram for now, open question, copy to RAM or adapt for NAND */
+#endif
+}
+#endif
projects / u-boot / blobdiff