*/
#include <common.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
#include <malloc.h>
#include <command.h>
#include <crc.h>
mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */
/*--------------------------------------------------------------------
- * GPIO's are alreay setup in cpu/ppc4xx/cpu_init.c
+ * GPIO's are alreay setup in arch/powerpc/cpu/ppc4xx/cpu_init.c
* via define from board config file.
*-------------------------------------------------------------------*/
int checkboard(void)
{
- char *s = getenv("serial#");
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
printf("Board: PCS440EP");
- if (s != NULL) {
+ if (i > 0) {
puts(", serial# ");
- puts(s);
+ puts(buf);
}
putc('\n');
return dram_size;
}
-/*************************************************************************
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller *hose)
-{
- unsigned long addr;
-
- /*-------------------------------------------------------------------------+
- | Set priority for all PLB3 devices to 0.
- | Set PLB3 arbiter to fair mode.
- +-------------------------------------------------------------------------*/
- mfsdr(SD0_AMP1, addr);
- mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(PLB3_ACR);
- mtdcr(PLB3_ACR, addr | 0x80000000);
-
- /*-------------------------------------------------------------------------+
- | Set priority for all PLB4 devices to 0.
- +-------------------------------------------------------------------------*/
- mfsdr(SD0_AMP0, addr);
- mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
- mtdcr(PLB4_ACR, addr);
-
- /*-------------------------------------------------------------------------+
- | Set Nebula PLB4 arbiter to fair mode.
- +-------------------------------------------------------------------------*/
- /* Segment0 */
- addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
- addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
- addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
- addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
- mtdcr(PLB0_ACR, addr);
-
- /* Segment1 */
- addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
- addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
- addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
- addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
- mtdcr(PLB1_ACR, addr);
-
- return 1;
-}
-#endif /* defined(CONFIG_PCI) */
-
-/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- /*--------------------------------------------------------------------------+
- * Set up Direct MMIO registers
- *--------------------------------------------------------------------------*/
- /*--------------------------------------------------------------------------+
- | PowerPC440 EP PCI Master configuration.
- | Map one 1Gig range of PLB/processor addresses to PCI memory space.
- | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
- | Use byte reversed out routines to handle endianess.
- | Make this region non-prefetchable.
- +--------------------------------------------------------------------------*/
- out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
-
- out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
- out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
-
- out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
-
- /*--------------------------------------------------------------------------+
- * Set up Configuration registers
- *--------------------------------------------------------------------------*/
-
- /* Program the board's subsystem id/vendor id */
- pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
- CONFIG_SYS_PCI_SUBSYS_VENDORID);
- pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
-
- /* Configure command register as bus master */
- pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
- /* 240nS PCI clock */
- pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
- /* No error reporting */
- pci_write_config_word(0, PCI_ERREN, 0);
-
- pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-/*************************************************************************
- * pci_master_init
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
-void pci_master_init(struct pci_controller *hose)
-{
- unsigned short temp_short;
-
- /*--------------------------------------------------------------------------+
- | Write the PowerPC440 EP PCI Configuration regs.
- | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
- | Enable PowerPC440 EP to act as a PCI memory target (PTM).
- +--------------------------------------------------------------------------*/
- pci_read_config_word(0, PCI_COMMAND, &temp_short);
- pci_write_config_word(0, PCI_COMMAND,
- temp_short | PCI_COMMAND_MASTER |
- PCI_COMMAND_MEMORY);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
-
/*************************************************************************
* hw_watchdog_reset
*
* "led" Commando for the U-Boot shell
*
************************************************************************/
-int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int rcode = 0, i;
ulong pattern = 0;
* "sha1" Commando for the U-Boot shell
*
************************************************************************/
-int do_sha1 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_sha1 (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int rcode = -1;
if (argc < 2) {
- usage:
- cmd_usage(cmdtp);
- return 1;
+usage:
+ return cmd_usage(cmdtp);
}
if (argc >= 3) {
projects / u-boot / blobdiff