Merge branch 'master' of git://git.denx.de/u-boot-video

[u-boot] / board / phytec / pcm051 / board.c

diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index f53c5bbd4b50f4e42781fabb13ac74f62e9902e4..1bf9d730e5b4eb4f50a5e946c2541b4a7455922c 100644 (file)
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -31,8 +31,6 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* MII mode defines */
-#define MII_MODE_ENABLE                0x0
-#define RGMII_MODE_ENABLE      0xA
 #define RMII_RGMII2_MODE_ENABLE        0x49
 
 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
@@ -51,25 +49,30 @@ const struct dpll_params *get_dpll_ddr_params(void)
        return &dpll_ddr;
 }
 
+#ifdef CONFIG_REV1
+const struct ctrl_ioregs ioregs = {
+       .cm0ioctl               = MT41J256M8HX15E_IOCTRL_VALUE,
+       .cm1ioctl               = MT41J256M8HX15E_IOCTRL_VALUE,
+       .cm2ioctl               = MT41J256M8HX15E_IOCTRL_VALUE,
+       .dt0ioctl               = MT41J256M8HX15E_IOCTRL_VALUE,
+       .dt1ioctl               = MT41J256M8HX15E_IOCTRL_VALUE,
+};
+
 static const struct ddr_data ddr3_data = {
        .datardsratio0 = MT41J256M8HX15E_RD_DQS,
        .datawdsratio0 = MT41J256M8HX15E_WR_DQS,
        .datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE,
        .datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA,
-       .datadldiff0 = PHY_DLL_LOCK_DIFF,
 };
 
 static const struct cmd_control ddr3_cmd_ctrl_data = {
        .cmd0csratio = MT41J256M8HX15E_RATIO,
-       .cmd0dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
        .cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
 
        .cmd1csratio = MT41J256M8HX15E_RATIO,
-       .cmd1dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
        .cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
 
        .cmd2csratio = MT41J256M8HX15E_RATIO,
-       .cmd2dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
        .cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
 };
 
@@ -84,6 +87,56 @@ static struct emif_regs ddr3_emif_reg_data = {
                                PHY_EN_DYN_PWRDN,
 };
 
+void sdram_init(void)
+{
+       config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
+                  &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+}
+#else
+const struct ctrl_ioregs ioregs = {
+       .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+       .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+       .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+       .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+       .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+static const struct ddr_data ddr3_data = {
+       .datardsratio0 = MT41K256M16HA125E_RD_DQS,
+       .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+       .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+       .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+       .cmd0csratio = MT41K256M16HA125E_RATIO,
+       .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+       .cmd1csratio = MT41K256M16HA125E_RATIO,
+       .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+       .cmd2csratio = MT41K256M16HA125E_RATIO,
+       .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+       .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+       .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+       .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+       .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+       .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+       .zq_config = MT41K256M16HA125E_ZQ_CFG,
+       .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
+                               PHY_EN_DYN_PWRDN,
+};
+
+void sdram_init(void)
+{
+       config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
+                  &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+}
+#endif
+
 void set_uart_mux_conf(void)
 {
        enable_uart0_pin_mux();
@@ -93,16 +146,10 @@ void set_mux_conf_regs(void)
 {
        /* Initalize the board header */
        enable_i2c0_pin_mux();
-       i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+       i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 
        enable_board_pin_mux();
 }
-
-void sdram_init(void)
-{
-       config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
-                       &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
-}
 #endif
 
 /*
@@ -110,7 +157,7 @@ void sdram_init(void)
  */
 int board_init(void)
 {
-       i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+       i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 
        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
@@ -129,13 +176,13 @@ static struct cpsw_slave_data cpsw_slaves[] = {
        {
                .slave_reg_ofs  = 0x208,
                .sliver_reg_ofs = 0xd80,
-               .phy_id         = 0,
+               .phy_addr       = 0,
                .phy_if         = PHY_INTERFACE_MODE_RGMII,
        },
        {
                .slave_reg_ofs  = 0x308,
                .sliver_reg_ofs = 0xdc0,
-               .phy_id         = 1,
+               .phy_addr       = 1,
                .phy_if         = PHY_INTERFACE_MODE_RGMII,
        },
 };
@@ -152,6 +199,7 @@ static struct cpsw_platform_data cpsw_data = {
        .ale_entries            = 1024,
        .host_port_reg_ofs      = 0x108,
        .hw_stats_reg_ofs       = 0x900,
+       .bd_ram_ofs             = 0x2000,
        .mac_control            = (1 << 5),
        .control                = cpsw_control,
        .host_port_num          = 0,
@@ -180,7 +228,7 @@ int board_eth_init(bd_t *bis)
                mac_addr[4] = mac_lo & 0xFF;
                mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 
-               if (is_valid_ether_addr(mac_addr))
+               if (is_valid_ethaddr(mac_addr))
                        eth_setenv_enetaddr("ethaddr", mac_addr);
                else
                        goto try_usbether;