* Copyright (C) 2013 Lemonage Software GmbH
* Author Lars Poeschel <poeschel@lemonage.de>
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
- * GNU General Public License for more details.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
DECLARE_GLOBAL_DATA_PTR;
-static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-#ifdef CONFIG_SPL_BUILD
-static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
-#endif
-
/* MII mode defines */
-#define MII_MODE_ENABLE 0x0
-#define RGMII_MODE_ENABLE 0xA
#define RMII_RGMII2_MODE_ENABLE 0x49
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-/* UART defines */
#ifdef CONFIG_SPL_BUILD
-#define UART_RESET (0x1 << 1)
-#define UART_CLK_RUNNING_MASK 0x1
-#define UART_SMART_IDLE_EN (0x1 << 0x3)
/* DDR RAM defines */
#define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */
-static void rtc32k_enable(void)
+#define OSC (V_OSCK/1000000)
+const struct dpll_params dpll_ddr = {
+ DDR_CLK_MHZ, OSC-1, 1, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_ddr_params(void)
{
- struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
-
- /*
- * Unlock the RTC's registers. For more details please see the
- * RTC_SS section of the TRM. In order to unlock we need to
- * write these specific values (keys) in this order.
- */
- writel(0x83e70b13, &rtc->kick0r);
- writel(0x95a4f1e0, &rtc->kick1r);
-
- /* Enable the RTC 32K OSC by setting bits 3 and 6. */
- writel((1 << 3) | (1 << 6), &rtc->osc);
+ return &dpll_ddr;
}
+#ifdef CONFIG_REV1
+const struct ctrl_ioregs ioregs = {
+ .cm0ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
+ .cm1ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
+ .cm2ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
+ .dt0ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
+ .dt1ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
+};
+
static const struct ddr_data ddr3_data = {
.datardsratio0 = MT41J256M8HX15E_RD_DQS,
.datawdsratio0 = MT41J256M8HX15E_WR_DQS,
.datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE,
.datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA,
- .datadldiff0 = PHY_DLL_LOCK_DIFF,
};
static const struct cmd_control ddr3_cmd_ctrl_data = {
.cmd0csratio = MT41J256M8HX15E_RATIO,
- .cmd0dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
.cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
.cmd1csratio = MT41J256M8HX15E_RATIO,
- .cmd1dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
.cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
.cmd2csratio = MT41J256M8HX15E_RATIO,
- .cmd2dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
.cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
};
.sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2,
.sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3,
.zq_config = MT41J256M8HX15E_ZQ_CFG,
- .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY,
+ .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY |
+ PHY_EN_DYN_PWRDN,
};
-#endif
-/*
- * early system init of muxing and clocks.
- */
-void s_init(void)
+void sdram_init(void)
{
- /*
- * WDT1 is already running when the bootloader gets control
- * Disable it to avoid "random" resets
- */
- writel(0xAAAA, &wdtimer->wdtwspr);
- while (readl(&wdtimer->wdtwwps) != 0x0)
- ;
- writel(0x5555, &wdtimer->wdtwspr);
- while (readl(&wdtimer->wdtwwps) != 0x0)
- ;
-
-#ifdef CONFIG_SPL_BUILD
- /* Setup the PLLs and the clocks for the peripherals */
- pll_init();
+ config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
+ &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+}
+#else
+const struct ctrl_ioregs ioregs = {
+ .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
- /* Enable RTC32K clock */
- rtc32k_enable();
+static const struct ddr_data ddr3_data = {
+ .datardsratio0 = MT41K256M16HA125E_RD_DQS,
+ .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+ .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+ .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
- /* UART softreset */
- u32 regval;
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+ .cmd0csratio = MT41K256M16HA125E_RATIO,
+ .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
- enable_uart0_pin_mux();
+ .cmd1csratio = MT41K256M16HA125E_RATIO,
+ .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
- regval = readl(&uart_base->uartsyscfg);
- regval |= UART_RESET;
- writel(regval, &uart_base->uartsyscfg);
- while ((readl(&uart_base->uartsyssts) & UART_CLK_RUNNING_MASK)
- != UART_CLK_RUNNING_MASK)
- ;
+ .cmd2csratio = MT41K256M16HA125E_RATIO,
+ .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
- /* Disable smart idle */
- regval = readl(&uart_base->uartsyscfg);
- regval |= UART_SMART_IDLE_EN;
- writel(regval, &uart_base->uartsyscfg);
+static struct emif_regs ddr3_emif_reg_data = {
+ .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+ .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+ .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+ .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+ .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+ .zq_config = MT41K256M16HA125E_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
+ PHY_EN_DYN_PWRDN,
+};
- gd = &gdata;
+void sdram_init(void)
+{
+ config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
+ &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+}
+#endif
- preloader_console_init();
+void set_uart_mux_conf(void)
+{
+ enable_uart0_pin_mux();
+}
+void set_mux_conf_regs(void)
+{
/* Initalize the board header */
enable_i2c0_pin_mux();
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
enable_board_pin_mux();
-
- config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
- &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
-#endif
}
+#endif
/*
* Basic board specific setup. Pinmux has been handled already.
*/
int board_init(void)
{
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
- gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
- .phy_id = 0,
+ .phy_addr = 0,
.phy_if = PHY_INTERFACE_MODE_RGMII,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
- .phy_id = 1,
+ .phy_addr = 1,
.phy_if = PHY_INTERFACE_MODE_RGMII,
},
};
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
#endif
#if defined(CONFIG_DRIVER_TI_CPSW) || \
- (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
+ (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
int board_eth_init(bd_t *bis)
{
int rv, n = 0;
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
- if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+ if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
printf("<ethaddr> not set. Reading from E-fuse\n");
/* try reading mac address from efuse */
mac_lo = readl(&cdev->macid0l);
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
- if (is_valid_ether_addr(mac_addr))
- eth_setenv_enetaddr("ethaddr", mac_addr);
+ if (is_valid_ethaddr(mac_addr))
+ eth_env_set_enetaddr("ethaddr", mac_addr);
else
goto try_usbether;
}
projects / u-boot / blobdiff