#include <common.h>
#include <ioports.h>
#include <mpc8260.h>
+#include <pci.h>
+#include <netdev.h>
/*
* I/O Port configuration table
/* Port B configuration */
{ /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* PB31 */
- /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* PB30 */
- /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* PB29 */
+ /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TX_ER */
+ /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_DV */
+ /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 TX_EN */
+#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
+#ifdef CONFIG_ETHER_ON_FCC2
+#error "SCC1 conflicts with FCC2"
+#endif
/* PB28 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */
- /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* PB27 */
- /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* PB26 */
- /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* PB25 */
- /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* PB24 */
- /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* PB23 */
- /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* PB22 */
- /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* PB21 */
- /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* PB20 */
- /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* PB19 */
- /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* PB18 */
+#else
+ /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_ER */
+#endif
+ /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 COL */
+ /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 CRS */
+ /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[3] */
+ /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[2] */
+ /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[1] */
+ /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[0] */
+ /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[0] */
+ /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[1] */
+ /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[2] */
+ /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[3] */
/* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
/* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
/* PB15 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* PC23 */
/* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK */
/* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXCK */
- /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* PC20 */
- /* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* PC19 */
- /* PC18 */ { 0, 1, 0, 0, 0, 0 }, /* PC18 */
+ /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK(2) */
+ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RXCK */
+ /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 TXCK */
/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
/* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */
/* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
ulong orx, volatile uchar * base)
{
volatile uchar c = 0xff;
- volatile ulong cnt, val;
- volatile ulong *addr;
volatile uint *sdmr_ptr;
volatile uint *orx_ptr;
+ ulong maxsize, size;
int i;
- ulong save[32]; /* to make test non-destructive */
- ulong maxsize;
/* We must be able to test a location outsize the maximum legal size
* to find out THAT we are outside; but this address still has to be
* accessing the SDRAM with a single-byte transaction."
*
* The appropriate BRx/ORx registers have already been set when we
- * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+ * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
*/
*sdmr_ptr = sdmr | PSDMR_OP_PREA;
*base = c;
*sdmr_ptr = sdmr | PSDMR_OP_MRW;
- *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */
+ *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
*base = c;
- /*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
- i = 0;
- for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
- addr = (volatile ulong *) base + cnt; /* pointer arith! */
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- addr = (volatile ulong *) base;
- save[i] = *addr;
- *addr = 0;
+ size = get_ram_size((long *)base, maxsize);
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
+ *orx_ptr = orx | ~(size - 1);
- for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt; /* pointer arith! */
- val = *addr;
- *addr = save[--i];
- if (val != ~cnt) {
- /* Write the actual size to ORx
- */
- *orx_ptr = orx | ~(cnt * sizeof (long) - 1);
- return (cnt * sizeof (long));
- }
- }
- return (maxsize);
+ return (size);
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
ulong size8, size9;
#endif
ulong psize = 32 * 1024 * 1024;
- memctl->memc_psrt = CFG_PSRT;
- memctl->memc_mptpr = CFG_MPTPR;
+ memctl->memc_psrt = CONFIG_SYS_PSRT;
+ memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-#ifndef CFG_RAMBOOT
- size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
- (uchar *) CFG_SDRAM_BASE);
- size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
- (uchar *) CFG_SDRAM_BASE);
+#ifndef CONFIG_SYS_RAMBOOT
+ size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+ (uchar *) CONFIG_SYS_SDRAM_BASE);
+ size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
+ (uchar *) CONFIG_SYS_SDRAM_BASE);
if (size8 < size9) {
psize = size9;
printf ("(60x:9COL) ");
} else {
- psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
- (uchar *) CFG_SDRAM_BASE);
+ psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+ (uchar *) CONFIG_SYS_SDRAM_BASE);
printf ("(60x:8COL) ");
}
#endif
return (psize);
}
-#if (CONFIG_COMMANDS & CFG_CMD_DOC)
-extern void doc_probe (ulong physadr);
+#if defined(CONFIG_CMD_DOC)
void doc_init (void)
{
- doc_probe (CFG_DOC_BASE);
+ doc_probe (CONFIG_SYS_DOC_BASE);
}
#endif
+
+#ifdef CONFIG_PCI
+struct pci_controller hose;
+
+extern void pci_mpc8250_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+ pci_mpc8250_init(&hose);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}