[MIPS] Fix dcache_status()

[u-boot] / board / pm856 / pm856.c

diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c
index a10075451e00ee905b51220172bc9a2123549aee..792d1e58905aca1c0037f1b5eb05ee8a245ff1f9 100644 (file)
--- a/board/pm856/pm856.c
+++ b/board/pm856/pm856.c
@@ -30,15 +30,13 @@
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
 #include <ioports.h>
-#include <spd.h>
+#include <spd_sdram.h>
 #include <miiphy.h>
 
 #if defined(CONFIG_DDR_ECC)
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
-extern long int spd_sdram(void);
-
 void local_bus_init(void);
 long int fixed_sdram(void);
 
@@ -231,14 +229,13 @@ long int
 initdram(int board_type)
 {
        long dram_size = 0;
-       extern long spd_sdram (void);
-       volatile immap_t *immap = (immap_t *)CFG_IMMR;
+
 
        puts("Initializing\n");
 
 #if defined(CONFIG_DDR_DLL)
        {
-           volatile ccsr_gur_t *gur= &immap->im_gur;
+           volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
            int i,x;
 
            x = 10;
@@ -287,9 +284,8 @@ initdram(int board_type)
 void
 local_bus_init(void)
 {
-       volatile immap_t *immap = (immap_t *)CFG_IMMR;
-       volatile ccsr_gur_t *gur = &immap->im_gur;
-       volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+       volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+       volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 
        uint clkdiv;
        uint lbc_hz;
@@ -382,8 +378,7 @@ int testdram (void)
 long int fixed_sdram (void)
 {
   #ifndef CFG_RAMBOOT
-       volatile immap_t *immap = (immap_t *)CFG_IMMR;
-       volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+       volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
 
        ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
        ddr->cs0_config = CFG_DDR_CS0_CONFIG;