mtd, ubi, ubifs: resync with Linux-3.14

[u-boot] / board / prodrive / alpr / nand.c

diff --git a/board/prodrive/alpr/nand.c b/board/prodrive/alpr/nand.c
index 20a80983073ba46bb6d13dbca6293d1de5ac72ae..5427de5634213ba427257ff07fd18cff79949a69 100644 (file)
--- a/board/prodrive/alpr/nand.c
+++ b/board/prodrive/alpr/nand.c
@@ -5,46 +5,30 @@
  * (C) Copyright 2006
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#if defined(CONFIG_CMD_NAND)
 
 #include <asm/processor.h>
 #include <nand.h>
 
 struct alpr_ndfc_regs {
-       u16 cmd[4];
-       u16 addr_wait;
-       u16 term;
-       u16 dummy;
-       u16 dummy2;
-       u16 data;
+       u8 cmd[4];
+       u8 addr_wait;
+       u8 term;
+       u8 dummy;
+       u8 dummy2;
+       u8 data;
 };
 
 static u8 hwctl;
 static struct alpr_ndfc_regs *alpr_ndfc = NULL;
 
-#define readb(addr)    (u8)(*(volatile u16 *)(addr))
-#define writeb(d,addr) *(volatile u16 *)(addr) = ((u16)(d))
+#define readb(addr)    (u8)(*(volatile u8 *)(addr))
+#define writeb(d,addr) *(volatile u8 *)(addr) = ((u8)(d))
 
 /*
  * The ALPR has a NAND Flash Controller (NDFC) that handles all accesses to
@@ -56,43 +40,24 @@ static struct alpr_ndfc_regs *alpr_ndfc = NULL;
  *
  * There are 2 NAND devices on the board, a Hynix HY27US08561A (1 GByte).
  */
-static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd)
-{
-       switch (cmd) {
-       case NAND_CTL_SETCLE:
-               hwctl |= 0x1;
-               break;
-       case NAND_CTL_CLRCLE:
-               hwctl &= ~0x1;
-               break;
-       case NAND_CTL_SETALE:
-               hwctl |= 0x2;
-               break;
-       case NAND_CTL_CLRALE:
-               hwctl &= ~0x2;
-               break;
-       case NAND_CTL_SETNCE:
-               break;
-       case NAND_CTL_CLRNCE:
-               writeb(0x00, &(alpr_ndfc->term));
-               break;
-       }
-}
-
-static void alpr_nand_write_byte(struct mtd_info *mtd, u_char byte)
+static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
-       struct nand_chip *nand = mtd->priv;
+       struct nand_chip *this = mtd->priv;
 
-       if (hwctl & 0x1)
-               /*
-                * IO_ADDR_W used as CMD[i] reg to support multiple NAND
-                * chips.
-                */
-               writeb(byte, nand->IO_ADDR_W);
-       else if (hwctl & 0x2) {
-               writeb(byte, &(alpr_ndfc->addr_wait));
-       } else
-               writeb(byte, &(alpr_ndfc->data));
+       if (ctrl & NAND_CTRL_CHANGE) {
+               if ( ctrl & NAND_CLE )
+                       hwctl |= 0x1;
+               else
+                       hwctl &= ~0x1;
+               if ( ctrl & NAND_ALE )
+                       hwctl |= 0x2;
+               else
+                       hwctl &= ~0x2;
+               if ( (ctrl & NAND_NCE) != NAND_NCE)
+                       writeb(0x00, &(alpr_ndfc->term));
+       }
+       if (cmd != NAND_CMD_NONE)
+               writeb(cmd, this->IO_ADDR_W);
 }
 
 static u_char alpr_nand_read_byte(struct mtd_info *mtd)
@@ -128,6 +93,7 @@ static void alpr_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
        }
 }
 
+#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
 static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
 {
        int i;
@@ -138,15 +104,14 @@ static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len
 
        return 0;
 }
+#endif
 
 static int alpr_nand_dev_ready(struct mtd_info *mtd)
 {
-       volatile u_char val;
-
        /*
         * Blocking read to wait for NAND to be ready
         */
-       val = readb(&(alpr_ndfc->addr_wait));
+       (void)readb(&(alpr_ndfc->addr_wait));
 
        /*
         * Return always true
@@ -154,20 +119,22 @@ static int alpr_nand_dev_ready(struct mtd_info *mtd)
        return 1;
 }
 
-void board_nand_init(struct nand_chip *nand)
+int board_nand_init(struct nand_chip *nand)
 {
-       alpr_ndfc = (struct alpr_ndfc_regs *)CFG_NAND_BASE;
+       alpr_ndfc = (struct alpr_ndfc_regs *)CONFIG_SYS_NAND_BASE;
 
-       nand->eccmode = NAND_ECC_SOFT;
+       nand->ecc.mode = NAND_ECC_SOFT;
 
        /* Reference hardware control function */
-       nand->hwcontrol  = alpr_nand_hwcontrol;
-       /* Set command delay time */
-       nand->write_byte = alpr_nand_write_byte;
+       nand->cmd_ctrl  = alpr_nand_hwcontrol;
        nand->read_byte  = alpr_nand_read_byte;
        nand->write_buf  = alpr_nand_write_buf;
        nand->read_buf   = alpr_nand_read_buf;
+#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
        nand->verify_buf = alpr_nand_verify_buf;
+#endif
        nand->dev_ready  = alpr_nand_dev_ready;
+
+       return 0;
 }
 #endif