#include "mpsc.h"
#include "64460.h"
#include "mv_regs.h"
+#include "p3mx.h"
DECLARE_GLOBAL_DATA_PTR;
#define DP(x)
#endif
-extern void flush_data_cache (void);
-extern void invalidate_l1_instruction_cache (void);
extern flash_info_t flash_info[];
/* ------------------------------------------------------------------------- */
/* this is the current GT register space location */
-/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
+/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
/* Unfortunately, we cant change it while we are in flash, so we initialize it
* to the "final" value. This means that any debug_led calls before
*/
void board_prebootm_init (void);
-unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
+unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
int display_mem_map (void);
+void set_led(int);
/* ------------------------------------------------------------------------- */
GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
- (stat & 0xffff0000) | CFG_PCI_IDSEL);
+ (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
}
if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /* if PCI-X */
GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
- (stat & 0xffff0000) | CFG_PCI_IDSEL);
+ (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
}
/* Enable master */
* in 64360 when writing to pci base go and overide remap automaticaly,
* in 64460 it doesn't
*/
- GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_SPACE >> 16);
- GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_SPACE_PCI >> 16);
- GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
+ GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_SPACE >> 16);
+ GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_SPACE_PCI >> 16);
+ GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
- GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
+ GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+ GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+ GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
- GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_SPACE >> 16);
- GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_SPACE_PCI >> 16);
- GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
+ GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_SPACE >> 16);
+ GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_SPACE_PCI >> 16);
+ GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
- GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
+ GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+ GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+ GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
/* PCI interface settings */
/* Timeout set to retry forever */
for (stat = 0; stat <= PCI_HOST1; stat++)
pciWriteConfigReg (stat,
PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
- SELF, CFG_GT_REGS);
+ SELF, CONFIG_SYS_GT_REGS);
#endif
}
/* cpu configuration register */
tmp = GTREGREAD (CPU_CONFIGURATION);
/* set the SINGLE_CPU bit see MV64460 */
-#ifndef CFG_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
+#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
tmp |= CPU_CONF_SINGLE_CPU;
#endif
tmp &= ~CPU_CONF_AACK_DELAY_2;
* that if it's not at the power-on location, it's where we put
* it last time. (huber)
*/
-
- my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
+ my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
#ifdef CONFIG_PCI
gt_pci_config ();
memoryMapDeviceSpace(DEVICE3, 0, 0);
GT_REG_WRITE(DEVICE_BANK3PARAMETERS, 0);
- GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_BOOT_PAR);
+ GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_BOOT_PAR);
gt_cpu_config();
/* MPP setup */
- GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
- GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
- GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
- GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
+ GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
+ GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
+ GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
+ GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
+
+ GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
- GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
+ set_led(LED_RED);
return 0;
}
u8 val;
icache_enable ();
-#ifdef CFG_L2
+#ifdef CONFIG_SYS_L2
l2cache_enable ();
#endif
#ifdef CONFIG_MPSC
* No diode, 250 ohm series resistor
*/
val = 0xa5;
- i2c_write(CFG_I2C_RTC_ADDR, 8, 1, &val, 1);
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
- /* now relocate the debug serial driver */
- mpsc_putchar += gd->reloc_off;
- mpsc_getchar += gd->reloc_off;
- mpsc_test_char += gd->reloc_off;
+ i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 8, 1, &val, 1);
return 0;
}
void after_reloc (ulong dest_addr, gd_t * gd)
{
- memoryMapDeviceSpace (BOOT_DEVICE, CFG_BOOT_SPACE, CFG_BOOT_SIZE);
+ memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE, CONFIG_SYS_BOOT_SIZE);
/* display_mem_map(); */
/* now, jump to the main U-Boot board init code */
+ set_led(LED_GREEN);
board_init_r (gd, dest_addr);
/* NOTREACHED */
}
{
char *s = getenv("serial#");
- printf("Board: %s", CFG_BOARD_NAME);
+ printf("Board: %s", CONFIG_SYS_BOARD_NAME);
if (s != NULL) {
puts(", serial# ");
return (0);
}
-/* utility functions */
-void debug_led (int led, int mode)
+void set_led(int col)
{
+ int tmp;
+ int on_pin;
+ int off_pin;
+
+ /* Program Mpp[22] as Gpp[22]
+ * Program Mpp[23] as Gpp[23]
+ */
+ tmp = GTREGREAD(MPP_CONTROL2);
+ tmp &= 0x00ffffff;
+ GT_REG_WRITE(MPP_CONTROL2,tmp);
+
+ /* Program Gpp[22] and Gpp[23] as output
+ */
+ tmp = GTREGREAD(GPP_IO_CONTROL);
+ tmp |= 0x00C00000;
+ GT_REG_WRITE(GPP_IO_CONTROL, tmp);
+
+ /* Program Gpp[22] and Gpp[23] as active high
+ */
+ tmp = GTREGREAD(GPP_LEVEL_CONTROL);
+ tmp &= 0xff3fffff;
+ GT_REG_WRITE(GPP_LEVEL_CONTROL, tmp);
+
+ switch(col) {
+ default:
+ case LED_OFF :
+ on_pin = 0;
+ off_pin = ((1 << 23) | (1 << 22));
+ break;
+ case LED_RED :
+ on_pin = (1 << 23);
+ off_pin = (1 << 22);
+ break;
+ case LED_GREEN :
+ on_pin = (1 << 22);
+ off_pin = (1 << 23);
+ break;
+ case LED_ORANGE :
+ on_pin = ((1 << 23) | (1 << 22));
+ off_pin = 0;
+ break;
+ }
+
+ /* Set output Gpp[22] and Gpp[23]
+ */
+ tmp = GTREGREAD(GPP_VALUE);
+ tmp |= on_pin;
+ tmp &= ~off_pin;
+ GT_REG_WRITE(GPP_VALUE, tmp);
}
int display_mem_map (void)
{
- int i, j;
+ int i;
unsigned int base, size, width;
+#ifdef CONFIG_PCI
+ int j;
+#endif
/* SDRAM */
printf ("SD (DDR) RAM\n");
/* DRAM check routines copied from gw8260 */
-#if defined (CFG_DRAM_TEST)
+#if defined (CONFIG_SYS_DRAM_TEST)
/*********************************************************************/
/* NAME: move64() - moves a double word (64-bit) */
}
-#if defined (CFG_DRAM_TEST_DATA)
+#if defined (CONFIG_SYS_DRAM_TEST_DATA)
unsigned long long pattern[] = {
0xaaaaaaaaaaaaaaaaULL,
/*********************************************************************/
int mem_test_data (void)
{
- unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
+ unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
unsigned long long temp64 = 0;
int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
int i;
return 0;
}
-#endif /* CFG_DRAM_TEST_DATA */
+#endif /* CONFIG_SYS_DRAM_TEST_DATA */
-#if defined (CFG_DRAM_TEST_ADDRESS)
+#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
/*********************************************************************/
/* NAME: mem_test_address() - test address lines */
/* */
int mem_test_address (void)
{
volatile unsigned int *pmem =
- (volatile unsigned int *) CFG_MEMTEST_START;
- const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
+ (volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
+ const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
unsigned int i;
/* write address to each location */
}
return 0;
}
-#endif /* CFG_DRAM_TEST_ADDRESS */
+#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
-#if defined (CFG_DRAM_TEST_WALK)
+#if defined (CONFIG_SYS_DRAM_TEST_WALK)
/*********************************************************************/
/* NAME: mem_march() - memory march */
/* */
}
return 0;
}
-#endif /* CFG_DRAM_TEST_WALK */
+#endif /* CONFIG_SYS_DRAM_TEST_WALK */
/*********************************************************************/
/* NAME: mem_test_walk() - a simple walking ones test */
{
unsigned long long mask;
volatile unsigned long long *pmem =
- (volatile unsigned long long *) CFG_MEMTEST_START;
- const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
+ (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
+ const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
unsigned int i;
int runaddress = 0;
int runwalk = 0;
-#ifdef CFG_DRAM_TEST_DATA
+#ifdef CONFIG_SYS_DRAM_TEST_DATA
s = getenv ("testdramdata");
rundata = (s && (*s == 'y')) ? 1 : 0;
#endif
-#ifdef CFG_DRAM_TEST_ADDRESS
+#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
s = getenv ("testdramaddress");
runaddress = (s && (*s == 'y')) ? 1 : 0;
#endif
-#ifdef CFG_DRAM_TEST_WALK
+#ifdef CONFIG_SYS_DRAM_TEST_WALK
s = getenv ("testdramwalk");
runwalk = (s && (*s == 'y')) ? 1 : 0;
#endif
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
printf ("Testing RAM from 0x%08x to 0x%08x ... "
"(don't panic... that will take a moment !!!!)\n",
- CFG_MEMTEST_START, CFG_MEMTEST_END);
-#ifdef CFG_DRAM_TEST_DATA
+ CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
+#ifdef CONFIG_SYS_DRAM_TEST_DATA
if (rundata == 1) {
printf ("Test DATA ... ");
if (mem_test_data () == 1) {
printf ("ok \n");
}
#endif
-#ifdef CFG_DRAM_TEST_ADDRESS
+#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
if (runaddress == 1) {
printf ("Test ADDRESS ... ");
if (mem_test_address () == 1) {
printf ("ok \n");
}
#endif
-#ifdef CFG_DRAM_TEST_WALK
+#ifdef CONFIG_SYS_DRAM_TEST_WALK
if (runwalk == 1) {
printf ("Test WALKING ONEs ... ");
if (mem_test_walk () == 1) {
return 0;
}
-#endif /* CFG_DRAM_TEST */
+#endif /* CONFIG_SYS_DRAM_TEST */
/* ronen - the below functions are used by the bootm function */
/* - we map the base register to fbe00000 (same mapping as in the LSP) */
projects / u-boot / blobdiff