ppc_4xx: Apply new HW register names

[u-boot] / board / prodrive / p3p440 / p3p440.c

diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c
index 20fd4dc2769cfa623c1b721dfcd08d0fc490ad76..9a078527609ea71caf505a1726902dc7c479c70e 100644 (file)
--- a/board/prodrive/p3p440/p3p440.c
+++ b/board/prodrive/p3p440/p3p440.c
@@ -209,28 +209,28 @@ void pci_target_init(struct pci_controller *hose)
        /*--------------------------------------------------------------------------+
         * Disable everything
         *--------------------------------------------------------------------------*/
-       out32r(PCIX0_PIM0SA, 0);        /* disable */
-       out32r(PCIX0_PIM1SA, 0);        /* disable */
-       out32r(PCIX0_PIM2SA, 0);        /* disable */
-       out32r(PCIX0_EROMBA, 0);        /* disable expansion rom */
+       out32r(PCIL0_PIM0SA, 0);        /* disable */
+       out32r(PCIL0_PIM1SA, 0);        /* disable */
+       out32r(PCIL0_PIM2SA, 0);        /* disable */
+       out32r(PCIL0_EROMBA, 0);        /* disable expansion rom */
 
        /*--------------------------------------------------------------------------+
         * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
         * options to not support sizes such as 128/256 MB.
         *--------------------------------------------------------------------------*/
-       out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
-       out32r(PCIX0_PIM0LAH, 0);
-       out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
+       out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
+       out32r(PCIL0_PIM0LAH, 0);
+       out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
 
-       out32r(PCIX0_BAR0, 0);
+       out32r(PCIL0_BAR0, 0);
 
        /*--------------------------------------------------------------------------+
         * Program the board's subsystem id/vendor id
         *--------------------------------------------------------------------------*/
-       out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
-       out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
+       out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+       out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 
-       out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+       out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
 }
 #endif                         /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */